Evan Green c42e2f0767 RISC-V: hwprobe: Add MISALIGNED_PERF key ... RISCV_HWPROBE_KEY_CPUPERF_0 was mistakenly flagged as a bitmask in hwprobe_key_is_bitmask(), when in reality it was an enum value. This causes problems when used in conjunction with RISCV_HWPROBE_WHICH_CPUS, since SLOW, FAST, and EMULATED have values whose bits overlap with each other. If the caller asked for the set of CPUs that was SLOW or EMULATED, the returned set would also include CPUs that were FAST. Introduce a new hwprobe key, RISCV_HWPROBE_KEY_MISALIGNED_PERF, which returns the same values in response to a direct query (with no flags), but is properly handled as an enumerated value. As a result, SLOW, FAST, and EMULATED are all correctly treated as distinct values under the new key when queried with the WHICH_CPUS flag. Leave the old key in place to avoid disturbing applications which may have already come to rely on the key, with or without its broken behavior with respect to the WHICH_CPUS flag. Fixes: e178bf146e ("RISC-V: hwprobe: Introduce which-cpus flag") Signed-off-by: Evan Green <evan@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20240809214444.3257596-2-evan@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-08-14 13:13:23 -07:00
..
acpi.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot-image-header.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
cmodx.rst	documentation: Fix riscv cmodx example	2024-07-01 10:50:18 -07:00
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
hwprobe.rst	RISC-V: hwprobe: Add MISALIGNED_PERF key	2024-08-14 13:13:23 -07:00
index.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
patch-acceptance.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
uabi.rst	Documentation: RISC-V: uabi: Only scalar misaligned loads are supported	2024-05-30 09:42:53 -07:00
vector.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
vm-layout.rst	riscv: Extend sv39 linear mapping max size to 128G	2024-07-26 05:50:50 -07:00