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91c960b005
A subsequent patch will add additional atomic operations. These new operations will use the same opcode field as the existing XADD, with the immediate discriminating different operations. In preparation, rename the instruction mode BPF_ATOMIC and start calling the zero immediate BPF_ADD. This is possible (doesn't break existing valid BPF progs) because the immediate field is currently reserved MBZ and BPF_ADD is zero. All uses are removed from the tree but the BPF_XADD definition is kept around to avoid breaking builds for people including kernel headers. Signed-off-by: Brendan Jackman <jackmanb@google.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20210114181751.768687-5-jackmanb@google.com
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
{
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"map element value illegal alu op, 1",
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.insns = {
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
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BPF_LD_MAP_FD(BPF_REG_1, 0),
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BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 2),
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BPF_ALU64_IMM(BPF_AND, BPF_REG_0, 8),
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BPF_ST_MEM(BPF_DW, BPF_REG_0, 0, 22),
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BPF_EXIT_INSN(),
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},
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.fixup_map_hash_48b = { 3 },
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.errstr = "R0 bitwise operator &= on pointer",
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.result = REJECT,
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},
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{
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"map element value illegal alu op, 2",
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.insns = {
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
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BPF_LD_MAP_FD(BPF_REG_1, 0),
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BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 2),
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BPF_ALU32_IMM(BPF_ADD, BPF_REG_0, 0),
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BPF_ST_MEM(BPF_DW, BPF_REG_0, 0, 22),
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BPF_EXIT_INSN(),
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},
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.fixup_map_hash_48b = { 3 },
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.errstr = "R0 32-bit pointer arithmetic prohibited",
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.result = REJECT,
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},
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{
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"map element value illegal alu op, 3",
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.insns = {
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
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BPF_LD_MAP_FD(BPF_REG_1, 0),
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BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 2),
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BPF_ALU64_IMM(BPF_DIV, BPF_REG_0, 42),
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BPF_ST_MEM(BPF_DW, BPF_REG_0, 0, 22),
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BPF_EXIT_INSN(),
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},
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.fixup_map_hash_48b = { 3 },
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.errstr = "R0 pointer arithmetic with /= operator",
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.result = REJECT,
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},
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{
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"map element value illegal alu op, 4",
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.insns = {
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
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BPF_LD_MAP_FD(BPF_REG_1, 0),
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BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 2),
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BPF_ENDIAN(BPF_FROM_BE, BPF_REG_0, 64),
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BPF_ST_MEM(BPF_DW, BPF_REG_0, 0, 22),
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BPF_EXIT_INSN(),
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},
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.fixup_map_hash_48b = { 3 },
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.errstr_unpriv = "R0 pointer arithmetic prohibited",
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.errstr = "invalid mem access 'inv'",
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.result = REJECT,
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.result_unpriv = REJECT,
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.flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS,
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},
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{
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"map element value illegal alu op, 5",
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.insns = {
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
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BPF_LD_MAP_FD(BPF_REG_1, 0),
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BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7),
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BPF_MOV64_IMM(BPF_REG_3, 4096),
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_10),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8),
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BPF_STX_MEM(BPF_DW, BPF_REG_2, BPF_REG_0, 0),
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BPF_ATOMIC_OP(BPF_DW, BPF_ADD, BPF_REG_2, BPF_REG_3, 0),
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BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_2, 0),
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BPF_ST_MEM(BPF_DW, BPF_REG_0, 0, 22),
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BPF_EXIT_INSN(),
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},
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.fixup_map_hash_48b = { 3 },
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.errstr_unpriv = "leaking pointer from stack off -8",
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.errstr = "R0 invalid mem access 'inv'",
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.result = REJECT,
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.flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS,
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},
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