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https://mirrors.bfsu.edu.cn/git/linux.git
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bf9095424d
* ultravisor communication device driver * fix TEID on terminating storage key ops RISC-V: * Added Sv57x4 support for G-stage page table * Added range based local HFENCE functions * Added remote HFENCE functions based on VCPU requests * Added ISA extension registers in ONE_REG interface * Updated KVM RISC-V maintainers entry to cover selftests support ARM: * Add support for the ARMv8.6 WFxT extension * Guard pages for the EL2 stacks * Trap and emulate AArch32 ID registers to hide unsupported features * Ability to select and save/restore the set of hypercalls exposed to the guest * Support for PSCI-initiated suspend in collaboration with userspace * GICv3 register-based LPI invalidation support * Move host PMU event merging into the vcpu data structure * GICv3 ITS save/restore fixes * The usual set of small-scale cleanups and fixes x86: * New ioctls to get/set TSC frequency for a whole VM * Allow userspace to opt out of hypercall patching * Only do MSR filtering for MSRs accessed by rdmsr/wrmsr AMD SEV improvements: * Add KVM_EXIT_SHUTDOWN metadata for SEV-ES * V_TSC_AUX support Nested virtualization improvements for AMD: * Support for "nested nested" optimizations (nested vVMLOAD/VMSAVE, nested vGIF) * Allow AVIC to co-exist with a nested guest running * Fixes for LBR virtualizations when a nested guest is running, and nested LBR virtualization support * PAUSE filtering for nested hypervisors Guest support: * Decoupling of vcpu_is_preempted from PV spinlocks -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmKN9M4UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNLeAf+KizAlQwxEehHHeNyTkZuKyMawrD6 zsqAENR6i1TxiXe7fDfPFbO2NR0ZulQopHbD9mwnHJ+nNw0J4UT7g3ii1IAVcXPu rQNRGMVWiu54jt+lep8/gDg0JvPGKVVKLhxUaU1kdWT9PhIOC6lwpP3vmeWkUfRi PFL/TMT0M8Nfryi0zHB0tXeqg41BiXfqO8wMySfBAHUbpv8D53D2eXQL6YlMM0pL 2quB1HxHnpueE5vj3WEPQ3PCdy1M2MTfCDBJAbZGG78Ljx45FxSGoQcmiBpPnhJr C6UGP4ZDWpml5YULUoA70k5ylCbP+vI61U4vUtzEiOjHugpPV5wFKtx5nw== =ozWx -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm updates from Paolo Bonzini: "S390: - ultravisor communication device driver - fix TEID on terminating storage key ops RISC-V: - Added Sv57x4 support for G-stage page table - Added range based local HFENCE functions - Added remote HFENCE functions based on VCPU requests - Added ISA extension registers in ONE_REG interface - Updated KVM RISC-V maintainers entry to cover selftests support ARM: - Add support for the ARMv8.6 WFxT extension - Guard pages for the EL2 stacks - Trap and emulate AArch32 ID registers to hide unsupported features - Ability to select and save/restore the set of hypercalls exposed to the guest - Support for PSCI-initiated suspend in collaboration with userspace - GICv3 register-based LPI invalidation support - Move host PMU event merging into the vcpu data structure - GICv3 ITS save/restore fixes - The usual set of small-scale cleanups and fixes x86: - New ioctls to get/set TSC frequency for a whole VM - Allow userspace to opt out of hypercall patching - Only do MSR filtering for MSRs accessed by rdmsr/wrmsr AMD SEV improvements: - Add KVM_EXIT_SHUTDOWN metadata for SEV-ES - V_TSC_AUX support Nested virtualization improvements for AMD: - Support for "nested nested" optimizations (nested vVMLOAD/VMSAVE, nested vGIF) - Allow AVIC to co-exist with a nested guest running - Fixes for LBR virtualizations when a nested guest is running, and nested LBR virtualization support - PAUSE filtering for nested hypervisors Guest support: - Decoupling of vcpu_is_preempted from PV spinlocks" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (199 commits) KVM: x86: Fix the intel_pt PMI handling wrongly considered from guest KVM: selftests: x86: Sync the new name of the test case to .gitignore Documentation: kvm: reorder ARM-specific section about KVM_SYSTEM_EVENT_SUSPEND x86, kvm: use correct GFP flags for preemption disabled KVM: LAPIC: Drop pending LAPIC timer injection when canceling the timer x86/kvm: Alloc dummy async #PF token outside of raw spinlock KVM: x86: avoid calling x86 emulator without a decoded instruction KVM: SVM: Use kzalloc for sev ioctl interfaces to prevent kernel data leak x86/fpu: KVM: Set the base guest FPU uABI size to sizeof(struct kvm_xsave) s390/uv_uapi: depend on CONFIG_S390 KVM: selftests: x86: Fix test failure on arch lbr capable platforms KVM: LAPIC: Trace LAPIC timer expiration on every vmentry KVM: s390: selftest: Test suppression indication on key prot exception KVM: s390: Don't indicate suppression on dirtying, failing memop selftests: drivers/s390x: Add uvdevice tests drivers/s390/char: Add Ultravisor io device MAINTAINERS: Update KVM RISC-V entry to cover selftests support RISC-V: KVM: Introduce ISA extension register RISC-V: KVM: Cleanup stale TLB entries when host CPU changes RISC-V: KVM: Add remote HFENCE functions based on VCPU requests ...
367 lines
9.7 KiB
C
367 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/handle_exit.c:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <asm/esr.h>
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#include <asm/exception.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_mmu.h>
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#include <asm/debug-monitors.h>
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#include <asm/traps.h>
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#include <kvm/arm_hypercalls.h>
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#define CREATE_TRACE_POINTS
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#include "trace_handle_exit.h"
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typedef int (*exit_handle_fn)(struct kvm_vcpu *);
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static void kvm_handle_guest_serror(struct kvm_vcpu *vcpu, u64 esr)
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{
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if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(NULL, esr))
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kvm_inject_vabt(vcpu);
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}
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static int handle_hvc(struct kvm_vcpu *vcpu)
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{
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int ret;
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trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0),
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kvm_vcpu_hvc_get_imm(vcpu));
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vcpu->stat.hvc_exit_stat++;
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ret = kvm_hvc_call_handler(vcpu);
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if (ret < 0) {
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vcpu_set_reg(vcpu, 0, ~0UL);
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return 1;
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}
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return ret;
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}
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static int handle_smc(struct kvm_vcpu *vcpu)
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{
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/*
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* "If an SMC instruction executed at Non-secure EL1 is
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* trapped to EL2 because HCR_EL2.TSC is 1, the exception is a
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* Trap exception, not a Secure Monitor Call exception [...]"
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*
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* We need to advance the PC after the trap, as it would
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* otherwise return to the same address...
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*/
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vcpu_set_reg(vcpu, 0, ~0UL);
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kvm_incr_pc(vcpu);
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return 1;
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}
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/*
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* Guest access to FP/ASIMD registers are routed to this handler only
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* when the system doesn't support FP/ASIMD.
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*/
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static int handle_no_fpsimd(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/**
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* kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event
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* instruction executed by a guest
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*
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* @vcpu: the vcpu pointer
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*
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* WFE[T]: Yield the CPU and come back to this vcpu when the scheduler
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* decides to.
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* WFI: Simply call kvm_vcpu_halt(), which will halt execution of
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* world-switches and schedule other host processes until there is an
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* incoming IRQ or FIQ to the VM.
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* WFIT: Same as WFI, with a timed wakeup implemented as a background timer
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*
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* WF{I,E}T can immediately return if the deadline has already expired.
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*/
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static int kvm_handle_wfx(struct kvm_vcpu *vcpu)
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{
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u64 esr = kvm_vcpu_get_esr(vcpu);
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if (esr & ESR_ELx_WFx_ISS_WFE) {
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trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true);
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vcpu->stat.wfe_exit_stat++;
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} else {
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trace_kvm_wfx_arm64(*vcpu_pc(vcpu), false);
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vcpu->stat.wfi_exit_stat++;
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}
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if (esr & ESR_ELx_WFx_ISS_WFxT) {
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if (esr & ESR_ELx_WFx_ISS_RV) {
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u64 val, now;
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now = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_TIMER_CNT);
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val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
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if (now >= val)
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goto out;
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} else {
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/* Treat WFxT as WFx if RN is invalid */
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esr &= ~ESR_ELx_WFx_ISS_WFxT;
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}
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}
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if (esr & ESR_ELx_WFx_ISS_WFE) {
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kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu));
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} else {
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if (esr & ESR_ELx_WFx_ISS_WFxT)
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vcpu->arch.flags |= KVM_ARM64_WFIT;
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kvm_vcpu_wfi(vcpu);
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}
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out:
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kvm_incr_pc(vcpu);
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return 1;
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}
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/**
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* kvm_handle_guest_debug - handle a debug exception instruction
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*
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* @vcpu: the vcpu pointer
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*
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* We route all debug exceptions through the same handler. If both the
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* guest and host are using the same debug facilities it will be up to
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* userspace to re-inject the correct exception for guest delivery.
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*
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* @return: 0 (while setting vcpu->run->exit_reason)
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*/
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static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu)
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{
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struct kvm_run *run = vcpu->run;
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u64 esr = kvm_vcpu_get_esr(vcpu);
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run->exit_reason = KVM_EXIT_DEBUG;
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run->debug.arch.hsr = lower_32_bits(esr);
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run->debug.arch.hsr_high = upper_32_bits(esr);
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run->flags = KVM_DEBUG_ARCH_HSR_HIGH_VALID;
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if (ESR_ELx_EC(esr) == ESR_ELx_EC_WATCHPT_LOW)
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run->debug.arch.far = vcpu->arch.fault.far_el2;
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return 0;
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}
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static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu)
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{
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u64 esr = kvm_vcpu_get_esr(vcpu);
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kvm_pr_unimpl("Unknown exception class: esr: %#016llx -- %s\n",
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esr, esr_get_class_string(esr));
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/*
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* Guest access to SVE registers should be routed to this handler only
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* when the system doesn't support SVE.
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*/
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static int handle_sve(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/*
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* Guest usage of a ptrauth instruction (which the guest EL1 did not turn into
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* a NOP). If we get here, it is that we didn't fixup ptrauth on exit, and all
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* that we can do is give the guest an UNDEF.
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*/
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static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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static exit_handle_fn arm_exit_handlers[] = {
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[0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec,
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[ESR_ELx_EC_WFx] = kvm_handle_wfx,
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[ESR_ELx_EC_CP15_32] = kvm_handle_cp15_32,
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[ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64,
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[ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32,
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[ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store,
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[ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id,
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[ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64,
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[ESR_ELx_EC_HVC32] = handle_hvc,
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[ESR_ELx_EC_SMC32] = handle_smc,
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[ESR_ELx_EC_HVC64] = handle_hvc,
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[ESR_ELx_EC_SMC64] = handle_smc,
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[ESR_ELx_EC_SYS64] = kvm_handle_sys_reg,
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[ESR_ELx_EC_SVE] = handle_sve,
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[ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_WATCHPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug,
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[ESR_ELx_EC_BRK64] = kvm_handle_guest_debug,
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[ESR_ELx_EC_FP_ASIMD] = handle_no_fpsimd,
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[ESR_ELx_EC_PAC] = kvm_handle_ptrauth,
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};
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static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
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{
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u64 esr = kvm_vcpu_get_esr(vcpu);
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u8 esr_ec = ESR_ELx_EC(esr);
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return arm_exit_handlers[esr_ec];
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}
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/*
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* We may be single-stepping an emulated instruction. If the emulation
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* has been completed in the kernel, we can return to userspace with a
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* KVM_EXIT_DEBUG, otherwise userspace needs to complete its
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* emulation first.
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*/
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static int handle_trap_exceptions(struct kvm_vcpu *vcpu)
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{
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int handled;
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/*
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* See ARM ARM B1.14.1: "Hyp traps on instructions
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* that fail their condition code check"
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*/
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if (!kvm_condition_valid(vcpu)) {
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kvm_incr_pc(vcpu);
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handled = 1;
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} else {
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exit_handle_fn exit_handler;
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exit_handler = kvm_get_exit_handler(vcpu);
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handled = exit_handler(vcpu);
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}
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return handled;
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}
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/*
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* Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
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* proper exit to userspace.
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*/
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int handle_exit(struct kvm_vcpu *vcpu, int exception_index)
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{
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struct kvm_run *run = vcpu->run;
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if (ARM_SERROR_PENDING(exception_index)) {
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/*
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* The SError is handled by handle_exit_early(). If the guest
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* survives it will re-execute the original instruction.
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*/
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return 1;
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}
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exception_index = ARM_EXCEPTION_CODE(exception_index);
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switch (exception_index) {
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case ARM_EXCEPTION_IRQ:
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return 1;
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case ARM_EXCEPTION_EL1_SERROR:
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return 1;
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case ARM_EXCEPTION_TRAP:
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return handle_trap_exceptions(vcpu);
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case ARM_EXCEPTION_HYP_GONE:
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/*
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* EL2 has been reset to the hyp-stub. This happens when a guest
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* is pre-emptied by kvm_reboot()'s shutdown call.
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*/
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run->exit_reason = KVM_EXIT_FAIL_ENTRY;
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return 0;
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case ARM_EXCEPTION_IL:
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/*
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* We attempted an illegal exception return. Guest state must
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* have been corrupted somehow. Give up.
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*/
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run->exit_reason = KVM_EXIT_FAIL_ENTRY;
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return -EINVAL;
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default:
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kvm_pr_unimpl("Unsupported exception type: %d",
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exception_index);
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run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
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return 0;
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}
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}
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/* For exit types that need handling before we can be preempted */
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void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index)
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{
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if (ARM_SERROR_PENDING(exception_index)) {
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if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) {
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u64 disr = kvm_vcpu_get_disr(vcpu);
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kvm_handle_guest_serror(vcpu, disr_to_esr(disr));
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} else {
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kvm_inject_vabt(vcpu);
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}
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return;
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}
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exception_index = ARM_EXCEPTION_CODE(exception_index);
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if (exception_index == ARM_EXCEPTION_EL1_SERROR)
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kvm_handle_guest_serror(vcpu, kvm_vcpu_get_esr(vcpu));
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}
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void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr,
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u64 elr_virt, u64 elr_phys,
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u64 par, uintptr_t vcpu,
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u64 far, u64 hpfar) {
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u64 elr_in_kimg = __phys_to_kimg(elr_phys);
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u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr_virt;
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u64 mode = spsr & PSR_MODE_MASK;
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u64 panic_addr = elr_virt + hyp_offset;
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if (mode != PSR_MODE_EL2t && mode != PSR_MODE_EL2h) {
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kvm_err("Invalid host exception to nVHE hyp!\n");
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} else if (ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
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(esr & ESR_ELx_BRK64_ISS_COMMENT_MASK) == BUG_BRK_IMM) {
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const char *file = NULL;
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unsigned int line = 0;
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/* All hyp bugs, including warnings, are treated as fatal. */
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if (!is_protected_kvm_enabled() ||
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IS_ENABLED(CONFIG_NVHE_EL2_DEBUG)) {
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struct bug_entry *bug = find_bug(elr_in_kimg);
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if (bug)
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bug_get_file_line(bug, &file, &line);
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}
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if (file)
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kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line);
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else
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kvm_err("nVHE hyp BUG at: [<%016llx>] %pB!\n", panic_addr,
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(void *)panic_addr);
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} else {
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kvm_err("nVHE hyp panic at: [<%016llx>] %pB!\n", panic_addr,
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(void *)panic_addr);
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}
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/*
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* Hyp has panicked and we're going to handle that by panicking the
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* kernel. The kernel offset will be revealed in the panic so we're
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* also safe to reveal the hyp offset as a debugging aid for translating
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* hyp VAs to vmlinux addresses.
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*/
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kvm_err("Hyp Offset: 0x%llx\n", hyp_offset);
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panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%016llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%016lx\n",
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spsr, elr_virt, esr, far, hpfar, par, vcpu);
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}
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