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4ba0b2c294
The FPGA manager class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code for the freeing of the class data structure and combines the create() and register() functions into a single register() or register_full() function. The register_full() function accepts an info data structure to provide flexibility in passing optional parameters. The register() function supports the current parameter list for users that don't require the use of optional parameters. The devm_fpga_mgr_register() function is retained, and the devm_fpga_mgr_register_full() function is added. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
333 lines
8.2 KiB
C
333 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Altera Passive Serial SPI Driver
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*
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* Copyright (c) 2017 United Western Technologies, Corporation
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*
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* Joshua Clayton <stillcompiling@gmail.com>
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*
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* Manage Altera FPGA firmware that is loaded over SPI using the passive
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* serial configuration method.
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* Firmware must be in binary "rbf" format.
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* Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
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* May work on other Altera FPGAs.
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*/
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#include <linux/bitrev.h>
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#include <linux/delay.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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#include <linux/sizes.h>
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enum altera_ps_devtype {
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CYCLONE5,
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ARRIA10,
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};
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struct altera_ps_data {
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enum altera_ps_devtype devtype;
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int status_wait_min_us;
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int status_wait_max_us;
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int t_cfg_us;
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int t_st2ck_us;
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};
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struct altera_ps_conf {
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struct gpio_desc *config;
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struct gpio_desc *confd;
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struct gpio_desc *status;
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struct spi_device *spi;
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const struct altera_ps_data *data;
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u32 info_flags;
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char mgr_name[64];
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};
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/* | Arria 10 | Cyclone5 | Stratix5 |
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* t_CF2ST0 | [; 600] | [; 600] | [; 600] |ns
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* t_CFG | [2;] | [2;] | [2;] |µs
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* t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
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* t_CF2ST1 | [; 3000] | [; 1506] | [; 1506] |µs
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* t_CF2CK | [3010;] | [1506;] | [1506;] |µs
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* t_ST2CK | [10;] | [2;] | [2;] |µs
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* t_CD2UM | [175; 830] | [175; 437] | [175; 437] |µs
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*/
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static struct altera_ps_data c5_data = {
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/* these values for Cyclone5 are compatible with Stratix5 */
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.devtype = CYCLONE5,
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.status_wait_min_us = 268,
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.status_wait_max_us = 1506,
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.t_cfg_us = 2,
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.t_st2ck_us = 2,
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};
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static struct altera_ps_data a10_data = {
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.devtype = ARRIA10,
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.status_wait_min_us = 268, /* min(t_STATUS) */
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.status_wait_max_us = 3000, /* max(t_CF2ST1) */
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.t_cfg_us = 2, /* max { min(t_CFG), max(tCF2ST0) } */
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.t_st2ck_us = 10, /* min(t_ST2CK) */
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};
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/* Array index is enum altera_ps_devtype */
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static const struct altera_ps_data *altera_ps_data_map[] = {
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&c5_data,
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&a10_data,
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};
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static const struct of_device_id of_ef_match[] = {
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{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
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{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, of_ef_match);
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static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
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{
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struct altera_ps_conf *conf = mgr->priv;
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if (gpiod_get_value_cansleep(conf->status))
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return FPGA_MGR_STATE_RESET;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static inline void altera_ps_delay(int delay_us)
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{
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if (delay_us > 10)
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usleep_range(delay_us, delay_us + 5);
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else
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udelay(delay_us);
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}
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static int altera_ps_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct altera_ps_conf *conf = mgr->priv;
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int min, max, waits;
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int i;
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conf->info_flags = info->flags;
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
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return -EINVAL;
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}
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gpiod_set_value_cansleep(conf->config, 1);
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/* wait min reset pulse time */
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altera_ps_delay(conf->data->t_cfg_us);
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if (!gpiod_get_value_cansleep(conf->status)) {
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dev_err(&mgr->dev, "Status pin failed to show a reset\n");
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return -EIO;
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}
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gpiod_set_value_cansleep(conf->config, 0);
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min = conf->data->status_wait_min_us;
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max = conf->data->status_wait_max_us;
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waits = max / min;
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if (max % min)
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waits++;
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/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
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for (i = 0; i < waits; i++) {
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usleep_range(min, min + 10);
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if (!gpiod_get_value_cansleep(conf->status)) {
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/* wait for min(t_ST2CK)*/
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altera_ps_delay(conf->data->t_st2ck_us);
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return 0;
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}
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}
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dev_err(&mgr->dev, "Status pin not ready.\n");
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return -EIO;
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}
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static void rev_buf(char *buf, size_t len)
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{
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u32 *fw32 = (u32 *)buf;
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size_t extra_bytes = (len & 0x03);
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const u32 *fw_end = (u32 *)(buf + len - extra_bytes);
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/* set buffer to lsb first */
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while (fw32 < fw_end) {
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*fw32 = bitrev8x4(*fw32);
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fw32++;
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}
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if (extra_bytes) {
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buf = (char *)fw_end;
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while (extra_bytes) {
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*buf = bitrev8(*buf);
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buf++;
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extra_bytes--;
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}
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}
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}
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static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct altera_ps_conf *conf = mgr->priv;
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const char *fw_data = buf;
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const char *fw_data_end = fw_data + count;
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while (fw_data < fw_data_end) {
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int ret;
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size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
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if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
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rev_buf((char *)fw_data, stride);
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ret = spi_write(conf->spi, fw_data, stride);
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if (ret) {
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dev_err(&mgr->dev, "spi error in firmware write: %d\n",
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ret);
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return ret;
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}
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fw_data += stride;
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}
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return 0;
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}
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static int altera_ps_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct altera_ps_conf *conf = mgr->priv;
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static const char dummy[] = {0};
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int ret;
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if (gpiod_get_value_cansleep(conf->status)) {
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dev_err(&mgr->dev, "Error during configuration.\n");
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return -EIO;
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}
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if (conf->confd) {
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if (!gpiod_get_raw_value_cansleep(conf->confd)) {
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dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
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return -EIO;
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}
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}
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/*
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* After CONF_DONE goes high, send two additional falling edges on DCLK
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* to begin initialization and enter user mode
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*/
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ret = spi_write(conf->spi, dummy, 1);
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if (ret) {
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dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct fpga_manager_ops altera_ps_ops = {
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.state = altera_ps_state,
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.write_init = altera_ps_write_init,
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.write = altera_ps_write,
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.write_complete = altera_ps_write_complete,
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};
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static const struct altera_ps_data *id_to_data(const struct spi_device_id *id)
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{
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kernel_ulong_t devtype = id->driver_data;
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const struct altera_ps_data *data;
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/* someone added a altera_ps_devtype without adding to the map array */
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if (devtype >= ARRAY_SIZE(altera_ps_data_map))
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return NULL;
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data = altera_ps_data_map[devtype];
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if (!data || data->devtype != devtype)
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return NULL;
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return data;
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}
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static int altera_ps_probe(struct spi_device *spi)
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{
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struct altera_ps_conf *conf;
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const struct of_device_id *of_id;
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struct fpga_manager *mgr;
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conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
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if (!conf)
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return -ENOMEM;
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if (spi->dev.of_node) {
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of_id = of_match_device(of_ef_match, &spi->dev);
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if (!of_id)
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return -ENODEV;
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conf->data = of_id->data;
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} else {
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conf->data = id_to_data(spi_get_device_id(spi));
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if (!conf->data)
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return -ENODEV;
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}
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conf->spi = spi;
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conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_LOW);
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if (IS_ERR(conf->config)) {
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dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
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PTR_ERR(conf->config));
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return PTR_ERR(conf->config);
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}
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conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
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if (IS_ERR(conf->status)) {
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dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
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PTR_ERR(conf->status));
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return PTR_ERR(conf->status);
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}
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conf->confd = devm_gpiod_get_optional(&spi->dev, "confd", GPIOD_IN);
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if (IS_ERR(conf->confd)) {
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dev_err(&spi->dev, "Failed to get confd gpio: %ld\n",
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PTR_ERR(conf->confd));
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return PTR_ERR(conf->confd);
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} else if (!conf->confd) {
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dev_warn(&spi->dev, "Not using confd gpio");
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}
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/* Register manager with unique name */
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snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
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dev_driver_string(&spi->dev), dev_name(&spi->dev));
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mgr = devm_fpga_mgr_register(&spi->dev, conf->mgr_name,
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&altera_ps_ops, conf);
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return PTR_ERR_OR_ZERO(mgr);
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}
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static const struct spi_device_id altera_ps_spi_ids[] = {
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{ "cyclone-ps-spi", CYCLONE5 },
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{ "fpga-passive-serial", CYCLONE5 },
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{ "fpga-arria10-passive-serial", ARRIA10 },
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{}
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};
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MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
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static struct spi_driver altera_ps_driver = {
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.driver = {
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.name = "altera-ps-spi",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(of_ef_match),
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},
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.id_table = altera_ps_spi_ids,
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.probe = altera_ps_probe,
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};
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module_spi_driver(altera_ps_driver)
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
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MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");
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