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c0adbd1cdf
There is nothing in use from log2.h/of_address.h, remove them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
448 lines
12 KiB
C
448 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018-2019 NXP.
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*
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* Limitations:
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* - The TPM counter and period counter are shared between
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* multiple channels, so all channels should use same period
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* settings.
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* - Changes to polarity cannot be latched at the time of the
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* next period start.
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* - Changing period and duty cycle together isn't atomic,
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* with the wrong timing it might happen that a period is
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* produced with old duty cycle but new period settings.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define PWM_IMX_TPM_PARAM 0x4
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#define PWM_IMX_TPM_GLOBAL 0x8
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#define PWM_IMX_TPM_SC 0x10
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#define PWM_IMX_TPM_CNT 0x14
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#define PWM_IMX_TPM_MOD 0x18
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#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
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#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
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#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
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#define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
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#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
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#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
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#define PWM_IMX_TPM_SC_CPWMS BIT(5)
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#define PWM_IMX_TPM_CnSC_CHF BIT(7)
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#define PWM_IMX_TPM_CnSC_MSB BIT(5)
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#define PWM_IMX_TPM_CnSC_MSA BIT(4)
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/*
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* The reference manual describes this field as two separate bits. The
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* semantic of the two bits isn't orthogonal though, so they are treated
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* together as a 2-bit field here.
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*/
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#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
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#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
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#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
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#define PWM_IMX_TPM_MOD_WIDTH 16
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#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
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struct imx_tpm_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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struct mutex lock;
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u32 user_count;
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u32 enable_count;
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u32 real_period;
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};
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struct imx_tpm_pwm_param {
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u8 prescale;
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u32 mod;
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u32 val;
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};
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static inline struct imx_tpm_pwm_chip *
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to_imx_tpm_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct imx_tpm_pwm_chip, chip);
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}
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/*
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* This function determines for a given pwm_state *state that a consumer
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* might request the pwm_state *real_state that eventually is implemented
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* by the hardware and the necessary register values (in *p) to achieve
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* this.
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*/
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static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
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struct imx_tpm_pwm_param *p,
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struct pwm_state *real_state,
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const struct pwm_state *state)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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u32 rate, prescale, period_count, clock_unit;
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u64 tmp;
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rate = clk_get_rate(tpm->clk);
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tmp = (u64)state->period * rate;
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clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
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if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
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prescale = 0;
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else
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prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
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if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
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return -ERANGE;
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p->prescale = prescale;
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period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
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p->mod = period_count;
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/* calculate real period HW can support */
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tmp = (u64)period_count << prescale;
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tmp *= NSEC_PER_SEC;
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real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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/*
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* if eventually the PWM output is inactive, either
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* duty cycle is 0 or status is disabled, need to
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* make sure the output pin is inactive.
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*/
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if (!state->enabled)
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real_state->duty_cycle = 0;
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else
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real_state->duty_cycle = state->duty_cycle;
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tmp = (u64)p->mod * real_state->duty_cycle;
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p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period);
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real_state->polarity = state->polarity;
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real_state->enabled = state->enabled;
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return 0;
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}
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static void pwm_imx_tpm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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u32 rate, val, prescale;
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u64 tmp;
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/* get period */
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state->period = tpm->real_period;
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/* get duty cycle */
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rate = clk_get_rate(tpm->clk);
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val = readl(tpm->base + PWM_IMX_TPM_SC);
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prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
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tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
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tmp = (tmp << prescale) * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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/* get polarity */
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val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
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if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
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state->polarity = PWM_POLARITY_INVERSED;
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else
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/*
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* Assume reserved values (2b00 and 2b11) to yield
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* normal polarity.
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*/
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state->polarity = PWM_POLARITY_NORMAL;
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/* get channel status */
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state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
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}
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/* this function is supposed to be called with mutex hold */
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static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
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struct imx_tpm_pwm_param *p,
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struct pwm_state *state,
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struct pwm_device *pwm)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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bool period_update = false;
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bool duty_update = false;
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u32 val, cmod, cur_prescale;
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unsigned long timeout;
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struct pwm_state c;
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if (state->period != tpm->real_period) {
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/*
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* TPM counter is shared by multiple channels, so
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* prescale and period can NOT be modified when
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* there are multiple channels in use with different
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* period settings.
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*/
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if (tpm->user_count > 1)
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return -EBUSY;
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val = readl(tpm->base + PWM_IMX_TPM_SC);
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cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
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cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
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if (cmod && cur_prescale != p->prescale)
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return -EBUSY;
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/* set TPM counter prescale */
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val &= ~PWM_IMX_TPM_SC_PS;
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val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
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writel(val, tpm->base + PWM_IMX_TPM_SC);
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/*
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* set period count:
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* if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
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* is updated when MOD register is written.
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*
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* if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
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* is latched into hardware when the next period starts.
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*/
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writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
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tpm->real_period = state->period;
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period_update = true;
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}
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pwm_imx_tpm_get_state(chip, pwm, &c);
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/* polarity is NOT allowed to be changed if PWM is active */
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if (c.enabled && c.polarity != state->polarity)
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return -EBUSY;
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if (state->duty_cycle != c.duty_cycle) {
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/*
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* set channel value:
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* if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
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* is updated when CnV register is written.
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*
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* if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
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* is latched into hardware when the next period starts.
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*/
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writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
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duty_update = true;
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}
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/* make sure MOD & CnV registers are updated */
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if (period_update || duty_update) {
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timeout = jiffies + msecs_to_jiffies(tpm->real_period /
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NSEC_PER_MSEC + 1);
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while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
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|| readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
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!= p->val) {
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if (time_after(jiffies, timeout))
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return -ETIME;
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cpu_relax();
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}
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}
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/*
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* polarity settings will enabled/disable output status
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* immediately, so if the channel is disabled, need to
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* make sure MSA/MSB/ELS are set to 0 which means channel
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* disabled.
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*/
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val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
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val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
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PWM_IMX_TPM_CnSC_MSB);
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if (state->enabled) {
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/*
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* set polarity (for edge-aligned PWM modes)
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*
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* ELS[1:0] = 2b10 yields normal polarity behaviour,
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* ELS[1:0] = 2b01 yields inversed polarity.
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* The other values are reserved.
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*/
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val |= PWM_IMX_TPM_CnSC_MSB;
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val |= (state->polarity == PWM_POLARITY_NORMAL) ?
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PWM_IMX_TPM_CnSC_ELS_NORMAL :
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PWM_IMX_TPM_CnSC_ELS_INVERSED;
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}
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writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
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/* control the counter status */
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if (state->enabled != c.enabled) {
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val = readl(tpm->base + PWM_IMX_TPM_SC);
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if (state->enabled) {
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if (++tpm->enable_count == 1)
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val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
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} else {
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if (--tpm->enable_count == 0)
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val &= ~PWM_IMX_TPM_SC_CMOD;
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}
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writel(val, tpm->base + PWM_IMX_TPM_SC);
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}
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return 0;
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}
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static int pwm_imx_tpm_apply(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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struct imx_tpm_pwm_param param;
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struct pwm_state real_state;
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int ret;
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ret = pwm_imx_tpm_round_state(chip, ¶m, &real_state, state);
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if (ret)
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return ret;
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mutex_lock(&tpm->lock);
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ret = pwm_imx_tpm_apply_hw(chip, ¶m, &real_state, pwm);
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mutex_unlock(&tpm->lock);
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return ret;
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}
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static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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mutex_lock(&tpm->lock);
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tpm->user_count++;
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mutex_unlock(&tpm->lock);
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return 0;
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}
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static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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mutex_lock(&tpm->lock);
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tpm->user_count--;
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mutex_unlock(&tpm->lock);
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}
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static const struct pwm_ops imx_tpm_pwm_ops = {
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.request = pwm_imx_tpm_request,
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.free = pwm_imx_tpm_free,
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.get_state = pwm_imx_tpm_get_state,
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.apply = pwm_imx_tpm_apply,
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.owner = THIS_MODULE,
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};
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static int pwm_imx_tpm_probe(struct platform_device *pdev)
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{
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struct imx_tpm_pwm_chip *tpm;
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int ret;
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u32 val;
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tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL);
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if (!tpm)
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return -ENOMEM;
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platform_set_drvdata(pdev, tpm);
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tpm->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(tpm->base))
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return PTR_ERR(tpm->base);
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tpm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(tpm->clk)) {
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ret = PTR_ERR(tpm->clk);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev,
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"failed to get PWM clock: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(tpm->clk);
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if (ret) {
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dev_err(&pdev->dev,
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"failed to prepare or enable clock: %d\n", ret);
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return ret;
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}
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tpm->chip.dev = &pdev->dev;
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tpm->chip.ops = &imx_tpm_pwm_ops;
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tpm->chip.base = -1;
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tpm->chip.of_xlate = of_pwm_xlate_with_flags;
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tpm->chip.of_pwm_n_cells = 3;
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/* get number of channels */
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val = readl(tpm->base + PWM_IMX_TPM_PARAM);
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tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
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mutex_init(&tpm->lock);
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ret = pwmchip_add(&tpm->chip);
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if (ret) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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clk_disable_unprepare(tpm->clk);
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}
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return ret;
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}
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static int pwm_imx_tpm_remove(struct platform_device *pdev)
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{
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struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev);
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int ret = pwmchip_remove(&tpm->chip);
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clk_disable_unprepare(tpm->clk);
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return ret;
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}
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static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev)
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{
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struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
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if (tpm->enable_count > 0)
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return -EBUSY;
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clk_disable_unprepare(tpm->clk);
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return 0;
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}
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static int __maybe_unused pwm_imx_tpm_resume(struct device *dev)
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{
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struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
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int ret = 0;
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ret = clk_prepare_enable(tpm->clk);
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if (ret)
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dev_err(dev,
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"failed to prepare or enable clock: %d\n",
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ret);
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return ret;
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}
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static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
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pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
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static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
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static struct platform_driver imx_tpm_pwm_driver = {
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.driver = {
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.name = "imx7ulp-tpm-pwm",
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.of_match_table = imx_tpm_pwm_dt_ids,
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.pm = &imx_tpm_pwm_pm,
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},
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.probe = pwm_imx_tpm_probe,
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.remove = pwm_imx_tpm_remove,
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};
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module_platform_driver(imx_tpm_pwm_driver);
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MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
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MODULE_DESCRIPTION("i.MX TPM PWM Driver");
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MODULE_LICENSE("GPL v2");
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