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Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
111 lines
2.4 KiB
Plaintext
111 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for SolidRun Armada 38x Microsom
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*/
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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* twice in u-boot.
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*/
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status = "okay";
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};
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};
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};
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};
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&bm {
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status = "okay";
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};
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&bm_bppi {
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status = "okay";
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};
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ð0 {
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/* ethernet@70000 */
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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phy = <&phy_dedicated>;
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phy-mode = "rgmii-id";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <1>;
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status = "okay";
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};
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&mdio {
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/*
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* Add the phy clock here, so the phy can be accessed to read its
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* IDs prior to binding with the driver.
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*/
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pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
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pinctrl-names = "default";
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phy_dedicated: ethernet-phy@0 {
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/*
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* Annoyingly, the marvell phy driver configures the LED
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* register, rather than preserving reset-loaded setting.
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* We undo that rubbish here.
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*/
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marvell,reg-init = <3 16 0 0x101e>;
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reg = <0>;
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};
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};
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&pinctrl {
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microsom_phy_clk_pins: microsom-phy-clk-pins {
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marvell,pins = "mpp45";
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marvell,function = "ref";
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};
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/* Optional eMMC */
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microsom_sdhci_pins: microsom-sdhci-pins {
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marvell,pins = "mpp21", "mpp28", "mpp37",
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"mpp38", "mpp39", "mpp40";
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marvell,function = "sd0";
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};
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};
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&spi1 {
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/* The microsom has an optional W25Q32 on board, connected to CS0 */
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pinctrl-0 = <&spi1_pins>;
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w25q32: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "w25q32", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <3000000>;
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status = "disabled";
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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