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c000273ebc
R3XX/R4XX AGP asic use the old PCI GART block, not the new PCIE GART. Make sure we pick the right GART when disabling AGP. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Acked-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
257 lines
6.6 KiB
C
257 lines
6.6 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "r420d.h"
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/* r420,r423,rv410 depends on : */
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void r100_pci_gart_disable(struct radeon_device *rdev);
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void r100_hdp_reset(struct radeon_device *rdev);
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void r100_mc_setup(struct radeon_device *rdev);
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int r100_gui_wait_for_idle(struct radeon_device *rdev);
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void r100_mc_disable_clients(struct radeon_device *rdev);
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void r300_vram_info(struct radeon_device *rdev);
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int r300_mc_wait_for_idle(struct radeon_device *rdev);
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int rv370_pcie_gart_enable(struct radeon_device *rdev);
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void rv370_pcie_gart_disable(struct radeon_device *rdev);
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/* This files gather functions specifics to :
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* r420,r423,rv410
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void r420_gpu_init(struct radeon_device *rdev);
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int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
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/*
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* MC
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*/
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int r420_mc_init(struct radeon_device *rdev)
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{
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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if (r420_debugfs_pipes_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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r420_gpu_init(rdev);
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r100_pci_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCIE) {
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rv370_pcie_gart_disable(rdev);
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}
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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printk(KERN_WARNING "[drm] Disabling AGP\n");
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rdev->flags &= ~RADEON_IS_AGP;
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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r100_mc_disable_clients(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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r100_mc_setup(rdev);
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return 0;
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}
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void r420_mc_fini(struct radeon_device *rdev)
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{
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if (rdev->flags & RADEON_IS_PCIE) {
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rv370_pcie_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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} else {
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r100_pci_gart_disable(rdev);
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radeon_gart_table_ram_free(rdev);
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}
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radeon_gart_fini(rdev);
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}
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/*
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* Global GPU functions
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*/
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void r420_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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void r420_pipes_init(struct radeon_device *rdev)
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{
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unsigned tmp;
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unsigned gb_pipe_select;
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unsigned num_pipes;
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/* GA_ENHANCE workaround TCL deadlock issue */
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WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
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/* get max number of pipes */
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gb_pipe_select = RREG32(0x402C);
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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rdev->num_gb_pipes = num_pipes;
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tmp = 0;
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switch (num_pipes) {
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default:
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/* force to 1 pipe */
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num_pipes = 1;
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case 1:
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tmp = (0 << 1);
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break;
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case 2:
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tmp = (3 << 1);
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break;
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case 3:
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tmp = (6 << 1);
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break;
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case 4:
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tmp = (7 << 1);
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break;
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}
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WREG32(0x42C8, (1 << num_pipes) - 1);
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/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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tmp |= (1 << 4) | (1 << 0);
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WREG32(0x4018, tmp);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = RREG32(0x170C);
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WREG32(0x170C, tmp | (1 << 31));
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WREG32(R300_RB2D_DSTCACHE_MODE,
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RREG32(R300_RB2D_DSTCACHE_MODE) |
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R300_DC_AUTOFLUSH_ENABLE |
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R300_DC_DC_DISABLE_IGNORE_PE);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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if (rdev->family == CHIP_RV530) {
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tmp = RREG32(RV530_GB_PIPE_SELECT2);
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if ((tmp & 3) == 3)
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rdev->num_z_pipes = 2;
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else
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rdev->num_z_pipes = 1;
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} else
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rdev->num_z_pipes = 1;
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DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
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rdev->num_gb_pipes, rdev->num_z_pipes);
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}
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void r420_gpu_init(struct radeon_device *rdev)
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{
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r100_hdp_reset(rdev);
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r420_pipes_init(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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/*
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* r420,r423,rv410 VRAM info
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*/
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void r420_vram_info(struct radeon_device *rdev)
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{
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r300_vram_info(rdev);
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t tmp;
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tmp = RREG32(R400_GB_PIPE_SELECT);
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seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
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tmp = RREG32(R300_GB_TILE_CONFIG);
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seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
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return 0;
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}
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static struct drm_info_list r420_pipes_info_list[] = {
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{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
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};
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#endif
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int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
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#else
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return 0;
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#endif
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}
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u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
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{
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u32 r;
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
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r = RREG32(R_0001FC_MC_IND_DATA);
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return r;
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}
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void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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{
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
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S_0001F8_MC_IND_WR_EN(1));
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WREG32(R_0001FC_MC_IND_DATA, v);
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}
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