Vincent Chen bff3ff5254 riscv: sifive: Apply errata "cip-1200" patch ... For certain SiFive CPUs, "sfence.vma addr" cannot exactly flush addr from TLB in the particular cases. The details could be found here: https://sifive.cdn.prismic.io/sifive/167a1a56-03f4-4615-a79e-b2a86153148f_FU740_errata_20210205.pdf In order to ensure the functionality, this patch uses the Alternative scheme to replace all "sfence.vma addr" with "sfence.vma" at runtime. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-04-26 08:24:58 -07:00
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errata_cip_453.S	riscv: sifive: Apply errata "cip-453" patch	2021-04-26 08:24:57 -07:00
errata.c	riscv: sifive: Apply errata "cip-1200" patch	2021-04-26 08:24:58 -07:00
Makefile	riscv: sifive: Apply errata "cip-453" patch	2021-04-26 08:24:57 -07:00