mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-06 02:24:14 +08:00
da7fa058a3
The hardware book says, the FCR is combined with a register called CHAR (it will trigger interrupt when a specific character is received). At first, I used lock/read/modify/write/unlock dance for the FCR to not affect the upper bits, but the CHAR is actually never used. It should not hurt to always clear the CHAR and to handle the FCR as a normal case. It can save the costly locking. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Denys Vlasenko <dvlasenk@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
293 lines
7.4 KiB
C
293 lines
7.4 KiB
C
/*
|
|
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <linux/clk.h>
|
|
#include <linux/console.h>
|
|
#include <linux/io.h>
|
|
#include <linux/module.h>
|
|
#include <linux/of.h>
|
|
#include <linux/platform_device.h>
|
|
|
|
#include "8250.h"
|
|
|
|
/* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */
|
|
#define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64
|
|
|
|
/*
|
|
* This hardware is similar to 8250, but its register map is a bit different:
|
|
* - MMIO32 (regshift = 2)
|
|
* - FCR is not at 2, but 3
|
|
* - LCR and MCR are not at 3 and 4, they share 4
|
|
* - Divisor latch at 9, no divisor latch access bit
|
|
*/
|
|
|
|
#define UNIPHIER_UART_REGSHIFT 2
|
|
|
|
/* bit[15:8] = CHAR (not used), bit[7:0] = FCR */
|
|
#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
|
|
/* bit[15:8] = LCR, bit[7:0] = MCR */
|
|
#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT))
|
|
/* Divisor Latch Register */
|
|
#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT))
|
|
|
|
struct uniphier8250_priv {
|
|
int line;
|
|
struct clk *clk;
|
|
spinlock_t atomic_write_lock;
|
|
};
|
|
|
|
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
|
static int __init uniphier_early_console_setup(struct earlycon_device *device,
|
|
const char *options)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
/* This hardware always expects MMIO32 register interface. */
|
|
device->port.iotype = UPIO_MEM32;
|
|
device->port.regshift = UNIPHIER_UART_REGSHIFT;
|
|
|
|
/*
|
|
* Do not touch the divisor register in early_serial8250_setup();
|
|
* we assume it has been initialized by a boot loader.
|
|
*/
|
|
device->baud = 0;
|
|
|
|
return early_serial8250_setup(device, options);
|
|
}
|
|
OF_EARLYCON_DECLARE(uniphier, "socionext,uniphier-uart",
|
|
uniphier_early_console_setup);
|
|
#endif
|
|
|
|
/*
|
|
* The register map is slightly different from that of 8250.
|
|
* IO callbacks must be overridden for correct access to FCR, LCR, and MCR.
|
|
*/
|
|
static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
|
|
{
|
|
unsigned int valshift = 0;
|
|
|
|
switch (offset) {
|
|
case UART_LCR:
|
|
valshift = 8;
|
|
/* fall through */
|
|
case UART_MCR:
|
|
offset = UNIPHIER_UART_LCR_MCR;
|
|
break;
|
|
default:
|
|
offset <<= UNIPHIER_UART_REGSHIFT;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* The return value must be masked with 0xff because LCR and MCR reside
|
|
* in the same register that must be accessed by 32-bit write/read.
|
|
* 8 or 16 bit access to this hardware result in unexpected behavior.
|
|
*/
|
|
return (readl(p->membase + offset) >> valshift) & 0xff;
|
|
}
|
|
|
|
static void uniphier_serial_out(struct uart_port *p, int offset, int value)
|
|
{
|
|
unsigned int valshift = 0;
|
|
bool normal = true;
|
|
|
|
switch (offset) {
|
|
case UART_FCR:
|
|
offset = UNIPHIER_UART_CHAR_FCR;
|
|
break;
|
|
case UART_LCR:
|
|
valshift = 8;
|
|
/* Divisor latch access bit does not exist. */
|
|
value &= ~UART_LCR_DLAB;
|
|
/* fall through */
|
|
case UART_MCR:
|
|
offset = UNIPHIER_UART_LCR_MCR;
|
|
normal = false;
|
|
break;
|
|
default:
|
|
offset <<= UNIPHIER_UART_REGSHIFT;
|
|
break;
|
|
}
|
|
|
|
if (normal) {
|
|
writel(value, p->membase + offset);
|
|
} else {
|
|
/*
|
|
* Special case: two registers share the same address that
|
|
* must be 32-bit accessed. As this is not longer atomic safe,
|
|
* take a lock just in case.
|
|
*/
|
|
struct uniphier8250_priv *priv = p->private_data;
|
|
unsigned long flags;
|
|
u32 tmp;
|
|
|
|
spin_lock_irqsave(&priv->atomic_write_lock, flags);
|
|
tmp = readl(p->membase + offset);
|
|
tmp &= ~(0xff << valshift);
|
|
tmp |= value << valshift;
|
|
writel(tmp, p->membase + offset);
|
|
spin_unlock_irqrestore(&priv->atomic_write_lock, flags);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This hardware does not have the divisor latch access bit.
|
|
* The divisor latch register exists at different address.
|
|
* Override dl_read/write callbacks.
|
|
*/
|
|
static int uniphier_serial_dl_read(struct uart_8250_port *up)
|
|
{
|
|
return readl(up->port.membase + UNIPHIER_UART_DLR);
|
|
}
|
|
|
|
static void uniphier_serial_dl_write(struct uart_8250_port *up, int value)
|
|
{
|
|
writel(value, up->port.membase + UNIPHIER_UART_DLR);
|
|
}
|
|
|
|
static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port,
|
|
struct uniphier8250_priv *priv)
|
|
{
|
|
int ret;
|
|
u32 prop;
|
|
struct device_node *np = dev->of_node;
|
|
|
|
ret = of_alias_get_id(np, "serial");
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get alias id\n");
|
|
return ret;
|
|
}
|
|
port->line = priv->line = ret;
|
|
|
|
/* Get clk rate through clk driver */
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(priv->clk)) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return PTR_ERR(priv->clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
port->uartclk = clk_get_rate(priv->clk);
|
|
|
|
/* Check for fifo size */
|
|
if (of_property_read_u32(np, "fifo-size", &prop) == 0)
|
|
port->fifosize = prop;
|
|
else
|
|
port->fifosize = UNIPHIER_UART_DEFAULT_FIFO_SIZE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int uniphier_uart_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct uart_8250_port up;
|
|
struct uniphier8250_priv *priv;
|
|
struct resource *regs;
|
|
void __iomem *membase;
|
|
int irq;
|
|
int ret;
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!regs) {
|
|
dev_err(dev, "failed to get memory resource\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
membase = devm_ioremap(dev, regs->start, resource_size(regs));
|
|
if (!membase)
|
|
return -ENOMEM;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get IRQ number\n");
|
|
return irq;
|
|
}
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
memset(&up, 0, sizeof(up));
|
|
|
|
ret = uniphier_of_serial_setup(dev, &up.port, priv);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
spin_lock_init(&priv->atomic_write_lock);
|
|
|
|
up.port.dev = dev;
|
|
up.port.private_data = priv;
|
|
up.port.mapbase = regs->start;
|
|
up.port.mapsize = resource_size(regs);
|
|
up.port.membase = membase;
|
|
up.port.irq = irq;
|
|
|
|
up.port.type = PORT_16550A;
|
|
up.port.iotype = UPIO_MEM32;
|
|
up.port.regshift = UNIPHIER_UART_REGSHIFT;
|
|
up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
|
|
up.capabilities = UART_CAP_FIFO;
|
|
|
|
up.port.serial_in = uniphier_serial_in;
|
|
up.port.serial_out = uniphier_serial_out;
|
|
up.dl_read = uniphier_serial_dl_read;
|
|
up.dl_write = uniphier_serial_dl_write;
|
|
|
|
ret = serial8250_register_8250_port(&up);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to register 8250 port\n");
|
|
clk_disable_unprepare(priv->clk);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int uniphier_uart_remove(struct platform_device *pdev)
|
|
{
|
|
struct uniphier8250_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
serial8250_unregister_port(priv->line);
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id uniphier_uart_match[] = {
|
|
{ .compatible = "socionext,uniphier-uart" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_uart_match);
|
|
|
|
static struct platform_driver uniphier_uart_platform_driver = {
|
|
.probe = uniphier_uart_probe,
|
|
.remove = uniphier_uart_remove,
|
|
.driver = {
|
|
.name = "uniphier-uart",
|
|
.of_match_table = uniphier_uart_match,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_uart_platform_driver);
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier UART driver");
|
|
MODULE_LICENSE("GPL");
|