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424d79183a
On a Rockchip rk3399-based board during suspend/resume testing, we found that we could get the console UART into a state where it would print this to the console a lot: serial8250: too much work for irq42 Followed eventually by: NMI watchdog: BUG: soft lockup - CPU#0 stuck for 11s! Upon debugging I found that we're in this state: iir = 0x000000cc lsr = 0x00000060 It appears that somehow we have a RX Timeout interrupt but there is no actual data present to receive. When we're in this state the UART driver claims that it handled the interrupt but it actually doesn't really do anything. This means that we keep getting the interrupt over and over again. Normally we don't actually need to do anything special to handle a RX Timeout interrupt. We'll notice that there is some data ready and we'll read it, which will end up clearing the RX Timeout. In this case we have a problem specifically because we got the RX TImeout without any data. Reading a bogus byte is confirmed to get us out of this state. It's unclear how exactly the UART got into this state, but it is known that the UART lines are essentially undriven and unpowered during suspend, so possibly during resume some garbage / half transmitted bits are seen on the line and put the UART into this state. The UART on the rk3399 is a DesignWare based 8250 UART. From mailing list posts, it appears that other people have run into similar problems with DesignWare based IP. Presumably this problem is unique to that IP, so I have placed the workaround there to avoid possibly of accidentally triggering bad behavior on other IP. Also note the RX Timeout behaves very differently in the DMA case, for for now the workaround is only applied to the non-DMA case. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
694 lines
17 KiB
C
694 lines
17 KiB
C
/*
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* Synopsys DesignWare 8250 driver.
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*
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* Copyright 2011 Picochip, Jamie Iles.
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* Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_reg.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/pm_runtime.h>
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#include <asm/byteorder.h>
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#include "8250.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_USR 0x1f /* UART Status Register */
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#define DW_UART_CPR 0xf4 /* Component Parameter Register */
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#define DW_UART_UCV 0xf8 /* UART Component Version */
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/* Component Parameter Register bits */
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#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
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#define DW_UART_CPR_AFCE_MODE (1 << 4)
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#define DW_UART_CPR_THRE_MODE (1 << 5)
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#define DW_UART_CPR_SIR_MODE (1 << 6)
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#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
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#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
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#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
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#define DW_UART_CPR_FIFO_STAT (1 << 10)
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#define DW_UART_CPR_SHADOW (1 << 11)
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#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
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#define DW_UART_CPR_DMA_EXTRA (1 << 13)
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#define DW_UART_CPR_FIFO_MODE (0xff << 16)
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/* Helper for fifo size calculation */
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#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
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/* DesignWare specific register fields */
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#define DW_UART_MCR_SIRE BIT(6)
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struct dw8250_data {
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u8 usr_reg;
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int line;
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int msr_mask_on;
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int msr_mask_off;
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struct clk *clk;
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struct clk *pclk;
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struct reset_control *rst;
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struct uart_8250_dma dma;
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unsigned int skip_autocfg:1;
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unsigned int uart_16550_compatible:1;
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};
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static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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/* Override any modem control signals if needed */
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if (offset == UART_MSR) {
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value |= d->msr_mask_on;
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value &= ~d->msr_mask_off;
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}
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return value;
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}
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static void dw8250_force_idle(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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serial8250_clear_and_reinit_fifos(up);
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(void)p->serial_in(p, UART_RX);
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}
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static void dw8250_check_lcr(struct uart_port *p, int value)
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{
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void __iomem *offset = p->membase + (UART_LCR << p->regshift);
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int tries = 1000;
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/* Make sure LCR write wasn't ignored */
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while (tries--) {
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unsigned int lcr = p->serial_in(p, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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return;
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dw8250_force_idle(p);
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#ifdef CONFIG_64BIT
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if (p->type == PORT_OCTEON)
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__raw_writeq(value & 0xff, offset);
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else
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#endif
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if (p->iotype == UPIO_MEM32)
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writel(value, offset);
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else if (p->iotype == UPIO_MEM32BE)
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iowrite32be(value, offset);
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else
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writeb(value, offset);
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}
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/*
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* FIXME: this deadlocks if port->lock is already held
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* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
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*/
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}
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static void dw8250_serial_out(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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writeb(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
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{
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unsigned int value = readb(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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#ifdef CONFIG_64BIT
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static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
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{
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unsigned int value;
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value = (u8)__raw_readq(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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value &= 0xff;
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__raw_writeq(value, p->membase + (offset << p->regshift));
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/* Read back to ensure register write ordering. */
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__raw_readq(p->membase + (UART_LCR << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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#endif /* CONFIG_64BIT */
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static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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writel(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
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{
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unsigned int value = readl(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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iowrite32be(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
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{
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unsigned int value = ioread32be(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static int dw8250_handle_irq(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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struct dw8250_data *d = p->private_data;
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unsigned int iir = p->serial_in(p, UART_IIR);
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unsigned int status;
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unsigned long flags;
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/*
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* There are ways to get Designware-based UARTs into a state where
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* they are asserting UART_IIR_RX_TIMEOUT but there is no actual
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* data available. If we see such a case then we'll do a bogus
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* read. If we don't do this then the "RX TIMEOUT" interrupt will
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* fire forever.
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*
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* This problem has only been observed so far when not in DMA mode
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* so we limit the workaround only to non-DMA mode.
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*/
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if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
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spin_lock_irqsave(&p->lock, flags);
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status = p->serial_in(p, UART_LSR);
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if (!(status & (UART_LSR_DR | UART_LSR_BI)))
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(void) p->serial_in(p, UART_RX);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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if (serial8250_handle_irq(p, iir))
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return 1;
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if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
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/* Clear the USR */
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(void)p->serial_in(p, d->usr_reg);
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return 1;
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}
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return 0;
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}
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static void
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dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
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{
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if (!state)
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pm_runtime_get_sync(port->dev);
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serial8250_do_pm(port, state, old);
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if (state)
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pm_runtime_put_sync_suspend(port->dev);
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}
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static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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struct dw8250_data *d = p->private_data;
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unsigned int rate;
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int ret;
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if (IS_ERR(d->clk) || !old)
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goto out;
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clk_disable_unprepare(d->clk);
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rate = clk_round_rate(d->clk, baud * 16);
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ret = clk_set_rate(d->clk, rate);
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clk_prepare_enable(d->clk);
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if (!ret)
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p->uartclk = rate;
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out:
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p->status &= ~UPSTAT_AUTOCTS;
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if (termios->c_cflag & CRTSCTS)
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p->status |= UPSTAT_AUTOCTS;
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serial8250_do_set_termios(p, termios, old);
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}
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static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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unsigned int mcr = p->serial_in(p, UART_MCR);
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if (up->capabilities & UART_CAP_IRDA) {
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if (termios->c_line == N_IRDA)
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mcr |= DW_UART_MCR_SIRE;
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else
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mcr &= ~DW_UART_MCR_SIRE;
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p->serial_out(p, UART_MCR, mcr);
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}
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serial8250_do_set_ldisc(p, termios);
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}
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/*
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* dw8250_fallback_dma_filter will prevent the UART from getting just any free
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* channel on platforms that have DMA engines, but don't have any channels
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* assigned to the UART.
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*
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* REVISIT: This is a work around for limitation in the DMA Engine API. Once the
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* core problem is fixed, this function is no longer needed.
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*/
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static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
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{
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return false;
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}
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static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
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{
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return param == chan->device->dev->parent;
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}
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static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
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{
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if (p->dev->of_node) {
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struct device_node *np = p->dev->of_node;
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int id;
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/* get index of serial line, if found in DT aliases */
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id = of_alias_get_id(np, "serial");
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if (id >= 0)
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p->line = id;
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#ifdef CONFIG_64BIT
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if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
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p->serial_in = dw8250_serial_inq;
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p->serial_out = dw8250_serial_outq;
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p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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data->usr_reg = 0x27;
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data->skip_autocfg = true;
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}
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#endif
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if (of_device_is_big_endian(p->dev->of_node)) {
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p->iotype = UPIO_MEM32BE;
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p->serial_in = dw8250_serial_in32be;
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p->serial_out = dw8250_serial_out32be;
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}
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} else if (has_acpi_companion(p->dev)) {
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const struct acpi_device_id *id;
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id = acpi_match_device(p->dev->driver->acpi_match_table,
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p->dev);
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if (id && !strcmp(id->id, "APMC0D08")) {
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p->iotype = UPIO_MEM32;
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p->regshift = 2;
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p->serial_in = dw8250_serial_in32;
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data->uart_16550_compatible = true;
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}
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}
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/* Platforms with iDMA */
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if (platform_get_resource_byname(to_platform_device(p->dev),
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IORESOURCE_MEM, "lpss_priv")) {
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data->dma.rx_param = p->dev->parent;
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data->dma.tx_param = p->dev->parent;
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data->dma.fn = dw8250_idma_filter;
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}
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}
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static void dw8250_setup_port(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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u32 reg;
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/*
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* If the Component Version Register returns zero, we know that
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* ADDITIONAL_FEATURES are not enabled. No need to go any further.
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*/
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if (p->iotype == UPIO_MEM32BE)
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reg = ioread32be(p->membase + DW_UART_UCV);
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else
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reg = readl(p->membase + DW_UART_UCV);
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if (!reg)
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return;
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dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
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(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
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if (p->iotype == UPIO_MEM32BE)
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reg = ioread32be(p->membase + DW_UART_CPR);
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else
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reg = readl(p->membase + DW_UART_CPR);
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if (!reg)
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return;
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/* Select the type based on fifo */
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if (reg & DW_UART_CPR_FIFO_MODE) {
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p->type = PORT_16550A;
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p->flags |= UPF_FIXED_TYPE;
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p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
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up->capabilities = UART_CAP_FIFO;
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}
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if (reg & DW_UART_CPR_AFCE_MODE)
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up->capabilities |= UART_CAP_AFE;
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if (reg & DW_UART_CPR_SIR_MODE)
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up->capabilities |= UART_CAP_IRDA;
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}
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static int dw8250_probe(struct platform_device *pdev)
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{
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struct uart_8250_port uart = {};
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struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int irq = platform_get_irq(pdev, 0);
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struct uart_port *p = &uart.port;
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struct device *dev = &pdev->dev;
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struct dw8250_data *data;
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int err;
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u32 val;
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if (!regs) {
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dev_err(dev, "no registers defined\n");
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return -EINVAL;
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}
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if (irq < 0) {
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if (irq != -EPROBE_DEFER)
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dev_err(dev, "cannot get irq\n");
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return irq;
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}
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spin_lock_init(&p->lock);
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p->mapbase = regs->start;
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p->irq = irq;
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p->handle_irq = dw8250_handle_irq;
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p->pm = dw8250_do_pm;
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p->type = PORT_8250;
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p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
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p->dev = dev;
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p->iotype = UPIO_MEM;
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p->serial_in = dw8250_serial_in;
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p->serial_out = dw8250_serial_out;
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p->set_ldisc = dw8250_set_ldisc;
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p->set_termios = dw8250_set_termios;
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p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
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if (!p->membase)
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return -ENOMEM;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->dma.fn = dw8250_fallback_dma_filter;
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data->usr_reg = DW_UART_USR;
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p->private_data = data;
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data->uart_16550_compatible = device_property_read_bool(dev,
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"snps,uart-16550-compatible");
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err = device_property_read_u32(dev, "reg-shift", &val);
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if (!err)
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p->regshift = val;
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|
|
|
err = device_property_read_u32(dev, "reg-io-width", &val);
|
|
if (!err && val == 4) {
|
|
p->iotype = UPIO_MEM32;
|
|
p->serial_in = dw8250_serial_in32;
|
|
p->serial_out = dw8250_serial_out32;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "dcd-override")) {
|
|
/* Always report DCD as active */
|
|
data->msr_mask_on |= UART_MSR_DCD;
|
|
data->msr_mask_off |= UART_MSR_DDCD;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "dsr-override")) {
|
|
/* Always report DSR as active */
|
|
data->msr_mask_on |= UART_MSR_DSR;
|
|
data->msr_mask_off |= UART_MSR_DDSR;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "cts-override")) {
|
|
/* Always report CTS as active */
|
|
data->msr_mask_on |= UART_MSR_CTS;
|
|
data->msr_mask_off |= UART_MSR_DCTS;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "ri-override")) {
|
|
/* Always report Ring indicator as inactive */
|
|
data->msr_mask_off |= UART_MSR_RI;
|
|
data->msr_mask_off |= UART_MSR_TERI;
|
|
}
|
|
|
|
/* Always ask for fixed clock rate from a property. */
|
|
device_property_read_u32(dev, "clock-frequency", &p->uartclk);
|
|
|
|
/* If there is separate baudclk, get the rate from it. */
|
|
data->clk = devm_clk_get(dev, "baudclk");
|
|
if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
|
|
data->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
if (!IS_ERR_OR_NULL(data->clk)) {
|
|
err = clk_prepare_enable(data->clk);
|
|
if (err)
|
|
dev_warn(dev, "could not enable optional baudclk: %d\n",
|
|
err);
|
|
else
|
|
p->uartclk = clk_get_rate(data->clk);
|
|
}
|
|
|
|
/* If no clock rate is defined, fail. */
|
|
if (!p->uartclk) {
|
|
dev_err(dev, "clock rate not defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
data->pclk = devm_clk_get(dev, "apb_pclk");
|
|
if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) {
|
|
err = -EPROBE_DEFER;
|
|
goto err_clk;
|
|
}
|
|
if (!IS_ERR(data->pclk)) {
|
|
err = clk_prepare_enable(data->pclk);
|
|
if (err) {
|
|
dev_err(dev, "could not enable apb_pclk\n");
|
|
goto err_clk;
|
|
}
|
|
}
|
|
|
|
data->rst = devm_reset_control_get_optional(dev, NULL);
|
|
if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
|
|
err = -EPROBE_DEFER;
|
|
goto err_pclk;
|
|
}
|
|
if (!IS_ERR(data->rst))
|
|
reset_control_deassert(data->rst);
|
|
|
|
dw8250_quirks(p, data);
|
|
|
|
/* If the Busy Functionality is not implemented, don't handle it */
|
|
if (data->uart_16550_compatible)
|
|
p->handle_irq = NULL;
|
|
|
|
if (!data->skip_autocfg)
|
|
dw8250_setup_port(p);
|
|
|
|
/* If we have a valid fifosize, try hooking up DMA */
|
|
if (p->fifosize) {
|
|
data->dma.rxconf.src_maxburst = p->fifosize / 4;
|
|
data->dma.txconf.dst_maxburst = p->fifosize / 4;
|
|
uart.dma = &data->dma;
|
|
}
|
|
|
|
data->line = serial8250_register_8250_port(&uart);
|
|
if (data->line < 0) {
|
|
err = data->line;
|
|
goto err_reset;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
|
|
err_reset:
|
|
if (!IS_ERR(data->rst))
|
|
reset_control_assert(data->rst);
|
|
|
|
err_pclk:
|
|
if (!IS_ERR(data->pclk))
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
err_clk:
|
|
if (!IS_ERR(data->clk))
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int dw8250_remove(struct platform_device *pdev)
|
|
{
|
|
struct dw8250_data *data = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
serial8250_unregister_port(data->line);
|
|
|
|
if (!IS_ERR(data->rst))
|
|
reset_control_assert(data->rst);
|
|
|
|
if (!IS_ERR(data->pclk))
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
if (!IS_ERR(data->clk))
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dw8250_suspend(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
serial8250_suspend_port(data->line);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw8250_resume(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
serial8250_resume_port(data->line);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM
|
|
static int dw8250_runtime_suspend(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
if (!IS_ERR(data->clk))
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
if (!IS_ERR(data->pclk))
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw8250_runtime_resume(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
if (!IS_ERR(data->pclk))
|
|
clk_prepare_enable(data->pclk);
|
|
|
|
if (!IS_ERR(data->clk))
|
|
clk_prepare_enable(data->clk);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops dw8250_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
|
|
SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct of_device_id dw8250_of_match[] = {
|
|
{ .compatible = "snps,dw-apb-uart" },
|
|
{ .compatible = "cavium,octeon-3860-uart" },
|
|
{ /* Sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw8250_of_match);
|
|
|
|
static const struct acpi_device_id dw8250_acpi_match[] = {
|
|
{ "INT33C4", 0 },
|
|
{ "INT33C5", 0 },
|
|
{ "INT3434", 0 },
|
|
{ "INT3435", 0 },
|
|
{ "80860F0A", 0 },
|
|
{ "8086228A", 0 },
|
|
{ "APMC0D08", 0},
|
|
{ "AMD0020", 0 },
|
|
{ "AMDI0020", 0 },
|
|
{ "HISI0031", 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
|
|
|
|
static struct platform_driver dw8250_platform_driver = {
|
|
.driver = {
|
|
.name = "dw-apb-uart",
|
|
.pm = &dw8250_pm_ops,
|
|
.of_match_table = dw8250_of_match,
|
|
.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
|
|
},
|
|
.probe = dw8250_probe,
|
|
.remove = dw8250_remove,
|
|
};
|
|
|
|
module_platform_driver(dw8250_platform_driver);
|
|
|
|
MODULE_AUTHOR("Jamie Iles");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
|
|
MODULE_ALIAS("platform:dw-apb-uart");
|