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5fe8667484
When any 8250 based driver sets up DMA and has UART_CAP_RPM capability enabled the device is left powered on after transfer is done. We need to schedule a device suspend operation when DMA completes the transfer. The patch is based on the work done by the reporter. Reported-by: Huiquan Zhong <huiquan.zhong@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
276 lines
6.6 KiB
C
276 lines
6.6 KiB
C
/*
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* 8250_dma.c - DMA Engine API support for 8250.c
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*
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* Copyright (C) 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_reg.h>
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#include <linux/dma-mapping.h>
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#include "8250.h"
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static void __dma_tx_complete(void *param)
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{
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struct uart_8250_port *p = param;
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struct uart_8250_dma *dma = p->dma;
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struct circ_buf *xmit = &p->port.state->xmit;
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unsigned long flags;
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int ret;
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dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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spin_lock_irqsave(&p->port.lock, flags);
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dma->tx_running = 0;
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xmit->tail += dma->tx_size;
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xmit->tail &= UART_XMIT_SIZE - 1;
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p->port.icount.tx += dma->tx_size;
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&p->port);
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ret = serial8250_tx_dma(p);
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if (ret) {
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p->ier |= UART_IER_THRI;
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serial_port_out(&p->port, UART_IER, p->ier);
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}
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spin_unlock_irqrestore(&p->port.lock, flags);
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}
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static void __dma_rx_complete(void *param)
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{
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struct uart_8250_port *p = param;
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struct uart_8250_dma *dma = p->dma;
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struct tty_port *tty_port = &p->port.state->port;
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struct dma_tx_state state;
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int count;
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dma->rx_running = 0;
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dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
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count = dma->rx_size - state.residue;
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tty_insert_flip_string(tty_port, dma->rx_buf, count);
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p->port.icount.rx += count;
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tty_flip_buffer_push(tty_port);
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}
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int serial8250_tx_dma(struct uart_8250_port *p)
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{
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struct uart_8250_dma *dma = p->dma;
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struct circ_buf *xmit = &p->port.state->xmit;
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struct dma_async_tx_descriptor *desc;
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int ret;
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if (dma->tx_running)
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return 0;
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if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
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/* We have been called from __dma_tx_complete() */
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serial8250_rpm_put_tx(p);
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return 0;
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}
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dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
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desc = dmaengine_prep_slave_single(dma->txchan,
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dma->tx_addr + xmit->tail,
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dma->tx_size, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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ret = -EBUSY;
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goto err;
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}
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dma->tx_running = 1;
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desc->callback = __dma_tx_complete;
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desc->callback_param = p;
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dma->tx_cookie = dmaengine_submit(desc);
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dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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dma_async_issue_pending(dma->txchan);
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if (dma->tx_err) {
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dma->tx_err = 0;
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if (p->ier & UART_IER_THRI) {
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p->ier &= ~UART_IER_THRI;
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serial_out(p, UART_IER, p->ier);
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}
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}
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return 0;
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err:
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dma->tx_err = 1;
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return ret;
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}
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int serial8250_rx_dma(struct uart_8250_port *p)
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{
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struct uart_8250_dma *dma = p->dma;
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struct dma_async_tx_descriptor *desc;
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if (dma->rx_running)
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return 0;
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desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
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dma->rx_size, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc)
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return -EBUSY;
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dma->rx_running = 1;
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desc->callback = __dma_rx_complete;
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desc->callback_param = p;
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dma->rx_cookie = dmaengine_submit(desc);
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dma_async_issue_pending(dma->rxchan);
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return 0;
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}
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void serial8250_rx_dma_flush(struct uart_8250_port *p)
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{
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struct uart_8250_dma *dma = p->dma;
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if (dma->rx_running) {
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dmaengine_pause(dma->rxchan);
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__dma_rx_complete(p);
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dmaengine_terminate_async(dma->rxchan);
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}
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}
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EXPORT_SYMBOL_GPL(serial8250_rx_dma_flush);
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int serial8250_request_dma(struct uart_8250_port *p)
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{
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struct uart_8250_dma *dma = p->dma;
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phys_addr_t rx_dma_addr = dma->rx_dma_addr ?
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dma->rx_dma_addr : p->port.mapbase;
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phys_addr_t tx_dma_addr = dma->tx_dma_addr ?
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dma->tx_dma_addr : p->port.mapbase;
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dma_cap_mask_t mask;
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struct dma_slave_caps caps;
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int ret;
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/* Default slave configuration parameters */
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dma->rxconf.direction = DMA_DEV_TO_MEM;
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dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma->rxconf.src_addr = rx_dma_addr + UART_RX;
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dma->txconf.direction = DMA_MEM_TO_DEV;
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dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma->txconf.dst_addr = tx_dma_addr + UART_TX;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* Get a channel for RX */
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dma->rxchan = dma_request_slave_channel_compat(mask,
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dma->fn, dma->rx_param,
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p->port.dev, "rx");
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if (!dma->rxchan)
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return -ENODEV;
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/* 8250 rx dma requires dmaengine driver to support pause/terminate */
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ret = dma_get_slave_caps(dma->rxchan, &caps);
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if (ret)
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goto release_rx;
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if (!caps.cmd_pause || !caps.cmd_terminate ||
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caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
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ret = -EINVAL;
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goto release_rx;
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}
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dmaengine_slave_config(dma->rxchan, &dma->rxconf);
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/* Get a channel for TX */
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dma->txchan = dma_request_slave_channel_compat(mask,
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dma->fn, dma->tx_param,
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p->port.dev, "tx");
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if (!dma->txchan) {
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ret = -ENODEV;
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goto release_rx;
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}
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/* 8250 tx dma requires dmaengine driver to support terminate */
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ret = dma_get_slave_caps(dma->txchan, &caps);
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if (ret)
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goto err;
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if (!caps.cmd_terminate) {
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ret = -EINVAL;
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goto err;
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}
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dmaengine_slave_config(dma->txchan, &dma->txconf);
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/* RX buffer */
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if (!dma->rx_size)
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dma->rx_size = PAGE_SIZE;
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dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
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&dma->rx_addr, GFP_KERNEL);
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if (!dma->rx_buf) {
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ret = -ENOMEM;
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goto err;
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}
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/* TX buffer */
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dma->tx_addr = dma_map_single(dma->txchan->device->dev,
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p->port.state->xmit.buf,
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UART_XMIT_SIZE,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
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dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
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dma->rx_buf, dma->rx_addr);
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ret = -ENOMEM;
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goto err;
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}
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dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
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return 0;
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err:
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dma_release_channel(dma->txchan);
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release_rx:
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dma_release_channel(dma->rxchan);
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return ret;
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}
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EXPORT_SYMBOL_GPL(serial8250_request_dma);
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void serial8250_release_dma(struct uart_8250_port *p)
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{
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struct uart_8250_dma *dma = p->dma;
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if (!dma)
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return;
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/* Release RX resources */
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dmaengine_terminate_sync(dma->rxchan);
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dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
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dma->rx_addr);
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dma_release_channel(dma->rxchan);
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dma->rxchan = NULL;
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/* Release TX resources */
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dmaengine_terminate_sync(dma->txchan);
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dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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dma_release_channel(dma->txchan);
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dma->txchan = NULL;
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dma->tx_running = 0;
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dev_dbg_ratelimited(p->port.dev, "dma channels released\n");
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}
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EXPORT_SYMBOL_GPL(serial8250_release_dma);
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