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393cae5f32
Start from ACE1.x, DOAISE is added to AC timing control register bit 5, it combines with DOAIS to get effective timing, and has the default value 1. The current code fills DOAIS, DACTQE and DODS bits to a variable initialized to zero, and updates the variable to AC timing control register. With this operation, We change DOAISE to 0, and force a much more aggressive timing. The timing is even unable to form a working waveform on SDA pin. This patch uses read-modify-write operation for the AC timing control register access, thus makes sure those bits not supposed and intended to change are not touched. Signed-off-by: Chao Song <chao.song@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20231127124735.2080562-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| amd_manager.c | ||
| amd_manager.h | ||
| bus_type.c | ||
| bus.c | ||
| bus.h | ||
| cadence_master.c | ||
| cadence_master.h | ||
| debugfs.c | ||
| dmi-quirks.c | ||
| generic_bandwidth_allocation.c | ||
| intel_ace2x_debugfs.c | ||
| intel_ace2x.c | ||
| intel_auxdevice.c | ||
| intel_auxdevice.h | ||
| intel_bus_common.c | ||
| intel_init.c | ||
| intel.c | ||
| intel.h | ||
| irq.c | ||
| irq.h | ||
| Kconfig | ||
| Makefile | ||
| master.c | ||
| mipi_disco.c | ||
| qcom.c | ||
| slave.c | ||
| stream.c | ||
| sysfs_local.h | ||
| sysfs_slave_dpn.c | ||
| sysfs_slave.c | ||