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Add support for common interface of the common clock and reset driver for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL, and the PISMU provides clock and reset functionality. Each drivers are provided in this patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp [sboyd@kernel.org: Add bitfield.h include to pll.c] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
37 lines
880 B
C
37 lines
880 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Toshiba ARM SoC reset controller driver
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#ifndef _VISCONTI_RESET_H_
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#define _VISCONTI_RESET_H_
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#include <linux/reset-controller.h>
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struct visconti_reset_data {
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u32 rson_offset;
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u32 rsoff_offset;
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u8 rs_idx;
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};
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struct visconti_reset {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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const struct visconti_reset_data *resets;
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spinlock_t *lock;
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};
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extern const struct reset_control_ops visconti_reset_ops;
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int visconti_register_reset_controller(struct device *dev,
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struct regmap *regmap,
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const struct visconti_reset_data *resets,
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unsigned int num_resets,
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const struct reset_control_ops *reset_ops,
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spinlock_t *lock);
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#endif /* _VISCONTI_RESET_H_ */
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