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e155a36607
- Migrate platform clk drivers to .remove_new() - Migrate i2c clk drivers to .probe() instead of .probe_new() - Remove CLK_SET_PARENT from all Mediatek MSDC core clocks - Add infra_ao reset support for Mediatek MT8188 SoCs - Align driver_data to i2c_device_id tables in some i2c clk drivers - Use device_get_match_data() in vc5 clk driver * clk-platform: clk: mediatek: Convert all remaining drivers to platform_driver's .remove_new() clk: mediatek: Make mtk_clk_pdev_remove() return void clk: mediatek: Make mtk_clk_simple_remove() return void * clk-i2c: clk: si521xx: Switch i2c driver back to use .probe() clk: Switch i2c drivers back to use .probe() * clk-mediatek: clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks clk: mediatek: fix of_iomap memory leak clk: mediatek: reset: add infra_ao reset support for MT8188 dt-bindings: reset: mt8188: add thermal reset control bit clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag clk: mediatek: Enable all MT8192 clocks by default * clk-i2cid: clk: rs9: Fix .driver_data content in i2c_device_id clk: vc7: Fix .driver_data content in i2c_device_id clk: vc5: Fix .driver_data content in i2c_device_id * clk-vc5: clk: vc7: Use device_get_match_data() instead of of_device_get_match_data() clk: vc5: Use device_get_match_data() instead of of_device_get_match_data()
219 lines
6.7 KiB
C
219 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <linux/of_address.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-fhctl.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#include "clk-pllfh.h"
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#define REGOFF_REF2USB 0x8
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#define REGOFF_HDMI_REF 0x40
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#define MT8173_PLL_FMAX (3000UL * MHZ)
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#define CON0_MT8173_RST_BAR BIT(24)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
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_pcw_shift, _div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = CON0_MT8173_RST_BAR, \
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.fmax = MT8173_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
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_pcw_shift) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
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NULL)
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static const struct mtk_pll_div_table mmpll_div_table[] = {
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{ .div = 0, .freq = MT8173_PLL_FMAX },
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{ .div = 1, .freq = 1000000000 },
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{ .div = 2, .freq = 702000000 },
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{ .div = 3, .freq = 253500000 },
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{ .div = 4, .freq = 126750000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
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21, 0x204, 24, 0x0, 0x204, 0),
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PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
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21, 0x214, 24, 0x0, 0x214, 0),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
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0x220, 4, 0x0, 0x224, 0),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
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0x230, 4, 0x0, 0x234, 14),
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PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,
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0x244, 0, mmpll_div_table),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
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PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
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PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
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PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
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PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
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};
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enum fh_pll_id {
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FH_ARMCA7PLL,
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FH_ARMCA15PLL,
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FH_MAINPLL,
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FH_MPLL,
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FH_MSDCPLL,
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FH_MMPLL,
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FH_VENCPLL,
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FH_TVDPLL,
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FH_VCODECPLL,
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FH_LVDSPLL,
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FH_MSDC2PLL,
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FH_NR_FH,
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};
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#define FH(_pllid, _fhid, _offset) { \
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.data = { \
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.pll_id = _pllid, \
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.fh_id = _fhid, \
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.fh_ver = FHCTL_PLLFH_V1, \
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.fhx_offset = _offset, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}, \
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}
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static struct mtk_pllfh_data pllfhs[] = {
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FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38),
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FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c),
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FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
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FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
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FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
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FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
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FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
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FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
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FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
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FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec),
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FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100),
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};
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static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
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{ .compatible = "mediatek,mt8173-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
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static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
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{
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const u8 *fhctl_node = "mediatek,mt8173-fhctl";
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data;
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void __iomem *base;
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struct clk_hw *hw;
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int r;
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base = of_iomap(node, 0);
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if (!base)
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return -ENOMEM;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (IS_ERR_OR_NULL(clk_data)) {
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iounmap(base);
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return -ENOMEM;
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}
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fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
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r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
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pllfhs, ARRAY_SIZE(pllfhs), clk_data);
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if (r)
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goto free_clk_data;
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hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
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if (IS_ERR(hw)) {
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r = PTR_ERR(hw);
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dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
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goto unregister_plls;
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}
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clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
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hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
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base + REGOFF_HDMI_REF, 16, 3,
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CLK_DIVIDER_POWER_OF_TWO, NULL);
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clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_ref2usb;
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return 0;
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unregister_ref2usb:
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mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
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unregister_plls:
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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iounmap(base);
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return r;
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}
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static void clk_mt8173_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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mtk_free_clk_data(clk_data);
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}
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static struct platform_driver clk_mt8173_apmixed_drv = {
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.probe = clk_mt8173_apmixed_probe,
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.remove_new = clk_mt8173_apmixed_remove,
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.driver = {
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.name = "clk-mt8173-apmixed",
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.of_match_table = of_match_clk_mt8173_apmixed,
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},
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};
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module_platform_driver(clk_mt8173_apmixed_drv);
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MODULE_DESCRIPTION("MediaTek MT8173 apmixed clocks driver");
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MODULE_LICENSE("GPL");
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