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bebb106a5a
If the page fault is caused by mmio, we can cache the mmio info, later, we do not need to walk guest page table and quickly know it is a mmio fault while we emulate the mmio instruction Signed-off-by: Xiao Guangrong <xiaoguangrong@cn.fujitsu.com> Signed-off-by: Avi Kivity <avi@redhat.com>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
#ifndef __KVM_X86_MMU_H
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#define __KVM_X86_MMU_H
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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#define PT64_PT_BITS 9
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#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
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#define PT32_PT_BITS 10
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#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
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#define PT_WRITABLE_SHIFT 1
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#define PT_PRESENT_MASK (1ULL << 0)
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#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
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#define PT_USER_MASK (1ULL << 2)
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#define PT_PWT_MASK (1ULL << 3)
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#define PT_PCD_MASK (1ULL << 4)
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#define PT_ACCESSED_SHIFT 5
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#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
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#define PT_DIRTY_MASK (1ULL << 6)
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#define PT_PAGE_SIZE_MASK (1ULL << 7)
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#define PT_PAT_MASK (1ULL << 7)
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#define PT_GLOBAL_MASK (1ULL << 8)
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#define PT64_NX_SHIFT 63
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#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
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#define PT_PAT_SHIFT 7
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#define PT_DIR_PAT_SHIFT 12
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#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
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#define PT32_DIR_PSE36_SIZE 4
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#define PT32_DIR_PSE36_SHIFT 13
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#define PT32_DIR_PSE36_MASK \
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(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
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#define PT64_ROOT_LEVEL 4
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#define PT32_ROOT_LEVEL 2
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#define PT32E_ROOT_LEVEL 3
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#define PT_PDPE_LEVEL 3
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#define PT_DIRECTORY_LEVEL 2
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#define PT_PAGE_TABLE_LEVEL 1
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#define PFERR_PRESENT_MASK (1U << 0)
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#define PFERR_WRITE_MASK (1U << 1)
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#define PFERR_USER_MASK (1U << 2)
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#define PFERR_RSVD_MASK (1U << 3)
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#define PFERR_FETCH_MASK (1U << 4)
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int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
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int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
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static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
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{
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return kvm->arch.n_max_mmu_pages -
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kvm->arch.n_used_mmu_pages;
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}
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static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
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{
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if (unlikely(kvm_mmu_available_pages(vcpu->kvm)< KVM_MIN_FREE_MMU_PAGES))
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__kvm_mmu_free_some_pages(vcpu);
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}
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static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
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{
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if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
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return 0;
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return kvm_mmu_load(vcpu);
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}
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static inline int is_present_gpte(unsigned long pte)
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{
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return pte & PT_PRESENT_MASK;
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}
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static inline int is_writable_pte(unsigned long pte)
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{
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return pte & PT_WRITABLE_MASK;
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}
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static inline bool is_write_protection(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
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}
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static inline bool check_write_user_access(struct kvm_vcpu *vcpu,
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bool write_fault, bool user_fault,
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unsigned long pte)
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{
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if (unlikely(write_fault && !is_writable_pte(pte)
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&& (user_fault || is_write_protection(vcpu))))
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return false;
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if (unlikely(user_fault && !(pte & PT_USER_MASK)))
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return false;
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return true;
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}
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#endif
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