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036a4b4b4d
Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1639747533-9778-1-git-send-email-abel.vesa@nxp.com
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018-2021 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#ifndef __IMX_CLK_SCU_H
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#define __IMX_CLK_SCU_H
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#include <linux/firmware/imx/sci.h>
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#include <linux/of.h>
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#define IMX_SCU_GPR_CLK_GATE BIT(0)
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#define IMX_SCU_GPR_CLK_DIV BIT(1)
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#define IMX_SCU_GPR_CLK_MUX BIT(2)
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struct imx_clk_scu_rsrc_table {
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const u32 *rsrc;
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u8 num;
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};
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extern struct list_head imx_scu_clks[];
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extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
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int imx_clk_scu_init(struct device_node *np,
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const struct imx_clk_scu_rsrc_table *data);
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struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
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void *data);
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struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
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const char * const *parents,
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int num_parents, u32 rsrc_id, u8 clk_type);
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struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
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const char * const *parents, int num_parents,
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u32 rsrc_id, u8 clk_type);
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void imx_clk_scu_unregister(void);
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struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, bool hw_gate);
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void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
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struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
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int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
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bool invert);
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static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
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u8 clk_type)
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{
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return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
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}
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static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
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int num_parents, u32 rsrc_id, u8 clk_type)
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{
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return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
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}
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static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, bool hw_gate)
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{
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return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg,
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bit_idx, hw_gate);
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}
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static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg,
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u8 bit_idx, bool hw_gate)
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{
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return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
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bit_idx, hw_gate);
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}
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static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
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u32 rsrc_id, u8 gpr_id, bool invert)
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{
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return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
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IMX_SCU_GPR_CLK_GATE, invert);
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}
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static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
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u32 rsrc_id, u8 gpr_id)
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{
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return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
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IMX_SCU_GPR_CLK_DIV, 0);
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}
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static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
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int num_parents, u32 rsrc_id, u8 gpr_id)
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{
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return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
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gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
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}
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#endif
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