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Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit). This patch implements struct iommu_ops for SMMU for the upper IOMMU API. This H/W module supports multiple virtual address spaces(domain x4), and manages 2 level H/W translation pagetable. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/*
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* IOMMU API for SMMU in Tegra30
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef MACH_SMMU_H
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#define MACH_SMMU_H
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enum smmu_hwgrp {
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HWGRP_AFI,
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HWGRP_AVPC,
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HWGRP_DC,
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HWGRP_DCB,
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HWGRP_EPP,
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HWGRP_G2,
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HWGRP_HC,
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HWGRP_HDA,
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HWGRP_ISP,
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HWGRP_MPE,
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HWGRP_NV,
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HWGRP_NV2,
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HWGRP_PPCS,
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HWGRP_SATA,
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HWGRP_VDE,
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HWGRP_VI,
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HWGRP_COUNT,
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HWGRP_END = ~0,
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};
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#define HWG_AFI (1 << HWGRP_AFI)
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#define HWG_AVPC (1 << HWGRP_AVPC)
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#define HWG_DC (1 << HWGRP_DC)
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#define HWG_DCB (1 << HWGRP_DCB)
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#define HWG_EPP (1 << HWGRP_EPP)
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#define HWG_G2 (1 << HWGRP_G2)
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#define HWG_HC (1 << HWGRP_HC)
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#define HWG_HDA (1 << HWGRP_HDA)
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#define HWG_ISP (1 << HWGRP_ISP)
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#define HWG_MPE (1 << HWGRP_MPE)
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#define HWG_NV (1 << HWGRP_NV)
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#define HWG_NV2 (1 << HWGRP_NV2)
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#define HWG_PPCS (1 << HWGRP_PPCS)
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#define HWG_SATA (1 << HWGRP_SATA)
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#define HWG_VDE (1 << HWGRP_VDE)
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#define HWG_VI (1 << HWGRP_VI)
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#endif /* MACH_SMMU_H */
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