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The declarations are actually required for the device definitions, and are still valid even if the dma controller is disabled: arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function) arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alan Ott <alan@signal11.us> Signed-off-by: Stephen Warren <swarren@nvidia.com>
152 lines
4.6 KiB
C
152 lines
4.6 KiB
C
/*
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* arch/arm/mach-tegra/include/mach/dma.h
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*
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* Copyright (c) 2008-2009, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __MACH_TEGRA_DMA_H
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#define __MACH_TEGRA_DMA_H
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#include <linux/list.h>
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#define TEGRA_DMA_REQ_SEL_CNTR 0
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#define TEGRA_DMA_REQ_SEL_I2S_2 1
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#define TEGRA_DMA_REQ_SEL_I2S_1 2
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#define TEGRA_DMA_REQ_SEL_SPD_I 3
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#define TEGRA_DMA_REQ_SEL_UI_I 4
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#define TEGRA_DMA_REQ_SEL_MIPI 5
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#define TEGRA_DMA_REQ_SEL_I2S2_2 6
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#define TEGRA_DMA_REQ_SEL_I2S2_1 7
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#define TEGRA_DMA_REQ_SEL_UARTA 8
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#define TEGRA_DMA_REQ_SEL_UARTB 9
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#define TEGRA_DMA_REQ_SEL_UARTC 10
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#define TEGRA_DMA_REQ_SEL_SPI 11
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#define TEGRA_DMA_REQ_SEL_AC97 12
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#define TEGRA_DMA_REQ_SEL_ACMODEM 13
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#define TEGRA_DMA_REQ_SEL_SL4B 14
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#define TEGRA_DMA_REQ_SEL_SL2B1 15
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#define TEGRA_DMA_REQ_SEL_SL2B2 16
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#define TEGRA_DMA_REQ_SEL_SL2B3 17
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#define TEGRA_DMA_REQ_SEL_SL2B4 18
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#define TEGRA_DMA_REQ_SEL_UARTD 19
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#define TEGRA_DMA_REQ_SEL_UARTE 20
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#define TEGRA_DMA_REQ_SEL_I2C 21
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#define TEGRA_DMA_REQ_SEL_I2C2 22
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#define TEGRA_DMA_REQ_SEL_I2C3 23
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#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
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#define TEGRA_DMA_REQ_SEL_OWR 25
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#define TEGRA_DMA_REQ_SEL_INVALID 31
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struct tegra_dma_req;
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struct tegra_dma_channel;
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enum tegra_dma_mode {
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TEGRA_DMA_SHARED = 1,
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TEGRA_DMA_MODE_CONTINOUS = 2,
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TEGRA_DMA_MODE_ONESHOT = 4,
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};
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enum tegra_dma_req_error {
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TEGRA_DMA_REQ_SUCCESS = 0,
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TEGRA_DMA_REQ_ERROR_ABORTED,
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TEGRA_DMA_REQ_INFLIGHT,
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};
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enum tegra_dma_req_buff_status {
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TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
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TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
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TEGRA_DMA_REQ_BUF_STATUS_FULL,
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};
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struct tegra_dma_req {
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struct list_head node;
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unsigned int modid;
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int instance;
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/* Called when the req is complete and from the DMA ISR context.
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* When this is called the req structure is no longer queued by
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* the DMA channel.
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*
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* State of the DMA depends on the number of req it has. If there are
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* no DMA requests queued up, then it will STOP the DMA. It there are
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* more requests in the DMA, then it will queue the next request.
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*/
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void (*complete)(struct tegra_dma_req *req);
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/* This is a called from the DMA ISR context when the DMA is still in
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* progress and is actively filling same buffer.
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*
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* In case of continuous mode receive, this threshold is 1/2 the buffer
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* size. In other cases, this will not even be called as there is no
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* hardware support for it.
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*
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* In the case of continuous mode receive, if there is next req already
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* queued, DMA programs the HW to use that req when this req is
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* completed. If there is no "next req" queued, then DMA ISR doesn't do
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* anything before calling this callback.
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*
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* This is mainly used by the cases, where the clients has queued
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* only one req and want to get some sort of DMA threshold
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* callback to program the next buffer.
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*
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*/
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void (*threshold)(struct tegra_dma_req *req);
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/* 1 to copy to memory.
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* 0 to copy from the memory to device FIFO */
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int to_memory;
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void *virt_addr;
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unsigned long source_addr;
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unsigned long dest_addr;
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unsigned long dest_wrap;
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unsigned long source_wrap;
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unsigned long source_bus_width;
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unsigned long dest_bus_width;
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unsigned long req_sel;
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unsigned int size;
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/* Updated by the DMA driver on the conpletion of the request. */
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int bytes_transferred;
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int status;
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/* DMA completion tracking information */
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int buffer_status;
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/* Client specific data */
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void *dev;
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};
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int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req);
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int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req);
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void tegra_dma_dequeue(struct tegra_dma_channel *ch);
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void tegra_dma_flush(struct tegra_dma_channel *ch);
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bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
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struct tegra_dma_req *req);
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bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
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struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
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void tegra_dma_free_channel(struct tegra_dma_channel *ch);
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int __init tegra_dma_init(void);
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#endif
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