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3bef2ac4bd
There is no rtc for the 98dx3236 and derivative SoCs. Disable the rtc node inherited from the armada-370-xp base. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
362 lines
8.5 KiB
Plaintext
362 lines
8.5 KiB
Plaintext
/*
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* Device Tree Include file for Marvell 98dx3236 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Contains definitions specific to the 98dx3236 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-370-xp.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Marvell 98DX3236 SoC";
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compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,98dx3236-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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clock-latency = <1000000>;
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};
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};
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
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MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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/*
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* 98DX3236 has 1 x1 PCIe unit Gen2.0
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*/
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pciec: pcie-controller@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
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pcie1: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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};
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internal-regs {
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sdramc@1400 {
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compatible = "marvell,armada-xp-sdram-controller";
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reg = <0x1400 0x500>;
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};
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L2: l2-cache@8000 {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-level = <2>;
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cache-unified;
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wt-override;
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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/* does not exist */
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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status = "disabled";
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};
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gpio2: gpio@18180 { /* rework some properties */
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <1>; /* only gpio #32 */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>;
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};
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systemc: system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,mv98dx3236-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,mv98dx3236-cpu-clock";
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reg = <0x18700 0x24>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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};
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corediv-clock@18740 {
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status = "disabled";
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};
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
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};
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ethernet@70000 {
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compatible = "marvell,armada-xp-neta";
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};
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ethernet@74000 {
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compatible = "marvell,armada-xp-neta";
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};
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xor1: xor@f0800 {
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compatible = "marvell,orion-xor";
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reg = <0xf0800 0x100
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0xf0a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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nand: nand@d0000 {
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clocks = <&dfx_coredivclk 0>;
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};
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xor0: xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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};
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dfx: dfx-server@ac000000 {
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compatible = "marvell,dfx-server", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
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reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
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coreclk: mvebu-sar@f8204 {
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compatible = "marvell,mv98dx3236-core-clock";
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reg = <0xf8204 0x4>;
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#clock-cells = <1>;
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};
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dfx_coredivclk: corediv-clock@f8268 {
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compatible = "marvell,mv98dx3236-corediv-clock";
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reg = <0xf8268 0xc>;
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#clock-cells = <1>;
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clocks = <&mainpll>;
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clock-output-names = "nand";
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};
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};
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switch: switch@a8000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
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pp0: packet-processor@0 {
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compatible = "marvell,prestera-98dx3236";
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reg = <0 0x4000000>;
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interrupts = <33>, <34>, <35>;
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dfx = <&dfx>;
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};
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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&i2c0 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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};
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&i2c1 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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&mpic {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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&rtc {
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status = "disabled";
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};
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&timer {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&watchdog {
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compatible = "marvell,armada-xp-wdt";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&cpurst {
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reg = <0x20800 0x20>;
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};
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&usb0 {
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clocks = <&gateclk 18>;
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};
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&usb1 {
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clocks = <&gateclk 19>;
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};
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&pinctrl {
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compatible = "marvell,98dx3236-pinctrl";
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spi0_pins: spi0-pins {
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marvell,pins = "mpp0", "mpp1",
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"mpp2", "mpp3";
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marvell,function = "spi0";
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};
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};
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&spi0 {
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compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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};
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&sdio {
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status = "disabled";
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};
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