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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
151 lines
4.3 KiB
C
151 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/video/geode/display_gx1.h
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* -- Geode GX1 display controller
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*
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* Copyright (C) 2005 Arcom Control Systems Ltd.
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*
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* Based on AMD's original 2.4 driver:
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* Copyright (C) 2004 Advanced Micro Devices, Inc.
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*/
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#ifndef __DISPLAY_GX1_H__
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#define __DISPLAY_GX1_H__
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unsigned gx1_gx_base(void);
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int gx1_frame_buffer_size(void);
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extern const struct geode_dc_ops gx1_dc_ops;
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/* GX1 configuration I/O registers */
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#define CONFIG_CCR3 0xc3
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# define CONFIG_CCR3_MAPEN 0x10
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#define CONFIG_GCR 0xb8
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/* Memory controller registers */
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#define MC_BANK_CFG 0x08
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# define MC_BCFG_DIMM0_SZ_MASK 0x00000700
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# define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
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# define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
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#define MC_GBASE_ADD 0x14
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# define MC_GADD_GBADD_MASK 0x000003ff
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/* Display controller registers */
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#define DC_UNLOCK 0x00
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# define DC_UNLOCK_CODE 0x00004758
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#define DC_GENERAL_CFG 0x04
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# define DC_GCFG_DFLE 0x00000001
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# define DC_GCFG_CURE 0x00000002
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# define DC_GCFG_VCLK_DIV 0x00000004
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# define DC_GCFG_PLNO 0x00000004
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# define DC_GCFG_PPC 0x00000008
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# define DC_GCFG_CMPE 0x00000010
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# define DC_GCFG_DECE 0x00000020
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# define DC_GCFG_DCLK_MASK 0x000000C0
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# define DC_GCFG_DCLK_DIV_1 0x00000080
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# define DC_GCFG_DFHPSL_MASK 0x00000F00
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# define DC_GCFG_DFHPSL_POS 8
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# define DC_GCFG_DFHPEL_MASK 0x0000F000
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# define DC_GCFG_DFHPEL_POS 12
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# define DC_GCFG_CIM_MASK 0x00030000
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# define DC_GCFG_CIM_POS 16
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# define DC_GCFG_FDTY 0x00040000
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# define DC_GCFG_RTPM 0x00080000
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# define DC_GCFG_DAC_RS_MASK 0x00700000
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# define DC_GCFG_DAC_RS_POS 20
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# define DC_GCFG_CKWR 0x00800000
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# define DC_GCFG_LDBL 0x01000000
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# define DC_GCFG_DIAG 0x02000000
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# define DC_GCFG_CH4S 0x04000000
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# define DC_GCFG_SSLC 0x08000000
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# define DC_GCFG_VIDE 0x10000000
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# define DC_GCFG_VRDY 0x20000000
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# define DC_GCFG_DPCK 0x40000000
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# define DC_GCFG_DDCK 0x80000000
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#define DC_TIMING_CFG 0x08
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# define DC_TCFG_FPPE 0x00000001
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# define DC_TCFG_HSYE 0x00000002
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# define DC_TCFG_VSYE 0x00000004
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# define DC_TCFG_BLKE 0x00000008
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# define DC_TCFG_DDCK 0x00000010
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# define DC_TCFG_TGEN 0x00000020
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# define DC_TCFG_VIEN 0x00000040
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# define DC_TCFG_BLNK 0x00000080
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# define DC_TCFG_CHSP 0x00000100
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# define DC_TCFG_CVSP 0x00000200
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# define DC_TCFG_FHSP 0x00000400
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# define DC_TCFG_FVSP 0x00000800
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# define DC_TCFG_FCEN 0x00001000
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# define DC_TCFG_CDCE 0x00002000
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# define DC_TCFG_PLNR 0x00002000
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# define DC_TCFG_INTL 0x00004000
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# define DC_TCFG_PXDB 0x00008000
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# define DC_TCFG_BKRT 0x00010000
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# define DC_TCFG_PSD_MASK 0x000E0000
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# define DC_TCFG_PSD_POS 17
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# define DC_TCFG_DDCI 0x08000000
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# define DC_TCFG_SENS 0x10000000
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# define DC_TCFG_DNA 0x20000000
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# define DC_TCFG_VNA 0x40000000
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# define DC_TCFG_VINT 0x80000000
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#define DC_OUTPUT_CFG 0x0C
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# define DC_OCFG_8BPP 0x00000001
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# define DC_OCFG_555 0x00000002
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# define DC_OCFG_PCKE 0x00000004
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# define DC_OCFG_FRME 0x00000008
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# define DC_OCFG_DITE 0x00000010
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# define DC_OCFG_2PXE 0x00000020
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# define DC_OCFG_2XCK 0x00000040
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# define DC_OCFG_2IND 0x00000080
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# define DC_OCFG_34ADD 0x00000100
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# define DC_OCFG_FRMS 0x00000200
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# define DC_OCFG_CKSL 0x00000400
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# define DC_OCFG_PRMP 0x00000800
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# define DC_OCFG_PDEL 0x00001000
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# define DC_OCFG_PDEH 0x00002000
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# define DC_OCFG_CFRW 0x00004000
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# define DC_OCFG_DIAG 0x00008000
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#define DC_FB_ST_OFFSET 0x10
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#define DC_CB_ST_OFFSET 0x14
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#define DC_CURS_ST_OFFSET 0x18
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#define DC_ICON_ST_OFFSET 0x1C
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#define DC_VID_ST_OFFSET 0x20
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#define DC_LINE_DELTA 0x24
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#define DC_BUF_SIZE 0x28
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#define DC_H_TIMING_1 0x30
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#define DC_H_TIMING_2 0x34
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#define DC_H_TIMING_3 0x38
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#define DC_FP_H_TIMING 0x3C
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#define DC_V_TIMING_1 0x40
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#define DC_V_TIMING_2 0x44
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#define DC_V_TIMING_3 0x48
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#define DC_FP_V_TIMING 0x4C
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#define DC_CURSOR_X 0x50
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#define DC_ICON_X 0x54
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#define DC_V_LINE_CNT 0x54
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#define DC_CURSOR_Y 0x58
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#define DC_ICON_Y 0x5C
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#define DC_SS_LINE_CMP 0x5C
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#define DC_CURSOR_COLOR 0x60
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#define DC_ICON_COLOR 0x64
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#define DC_BORDER_COLOR 0x68
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#define DC_DFIFO_DIAG 0x78
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#define DC_CFIFO_DIAG 0x7C
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#endif /* !__DISPLAY_GX1_H__ */
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