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* Support for ACPI. * Various cleanups to the ISA string parsing, including making them case-insensitive * Support for the vector extension. * Support for independent irq/softirq stacks. * Our CPU DT binding now has "unevaluatedProperties: false" -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmSe70ATHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiWNPD/0ZfSdQ0A/gMVOzAD4zFKPEqQ6ffW2V Zy6Jo7UDNqKsiai7QA4XB1uyYIv/y1yUKJ0oeBVcA9Nzyq+TW9QDcApDBTabxAUI agY19YKw6VVZ+p7I9sMsf6EbdJdkNfSAzcQACPxb4ScEoaf9X+oAK5qgXuRuWluh qQuVkkJlgWc/t1cuUkrRdJmHQYvjP3zL7z4o344q2IVpXJkNNu0GeP+HbF8BYKcA +I/TTA5JY3kCIaxkpF2rU6pE6T5T9xrPmRYZ7bZoPUPnbL+M8As/jx3ym52Y4WGp kf8pgkxixOjU64kVJOH66CA8GaOiaAH/ptjQb0ZmCaGrHhr7aOT9HrkX4rU1lS8T stPphfM4gGPcCoPgRqSl+mEhBzjII8maOBLtbricAoQi6efRq8fzoOGaif/QpCbc 6n0LGS4nQPGVyD3rAPfHxxfrlGJR+SsgyDvjZoDhqauFglims14GnK+eBeO8zrui Aj/uuAS63VIYprJWC1NOBJlU2WKZiOGhCANpZ6W6SH21PYn2WjsVILqaGh+WN8ZO KOHxZNaN8fQag0Yg7oNAUb7l6S0DHYtJIksFnFW2Rf2+VT58RAMYRQbpbhr7Tqr+ jLgIR8PkFrBERHE49IqLGhAxGDnNzAUysMRw9pIk7WIre2Jt4wPqUdl+ee+5ErIX jiYfSFZw9q28UA== =Fpq8 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for ACPI - Various cleanups to the ISA string parsing, including making them case-insensitive - Support for the vector extension - Support for independent irq/softirq stacks - Our CPU DT binding now has "unevaluatedProperties: false" * tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (78 commits) riscv: hibernate: remove WARN_ON in save_processor_state dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema riscv: stack: Add config of thread stack size riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing perf: RISC-V: Limit the number of counters returned from SBI riscv: replace deprecated scall with ecall riscv: uprobes: Restore thread.bad_cause riscv: mm: try VMA lock-based page fault handling first riscv: mm: Pre-allocate PGD entries for vmalloc/modules area RISC-V: hwprobe: Expose Zba, Zbb, and Zbs RISC-V: Track ISA extensions per hart ...
101 lines
2.7 KiB
Makefile
101 lines
2.7 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the RISC-V Linux kernel
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#
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ifdef CONFIG_FTRACE
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CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
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CFLAGS_REMOVE_patch.o = $(CC_FLAGS_FTRACE)
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CFLAGS_REMOVE_sbi.o = $(CC_FLAGS_FTRACE)
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endif
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CFLAGS_syscall_table.o += $(call cc-option,-Wno-override-init,)
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CFLAGS_compat_syscall_table.o += $(call cc-option,-Wno-override-init,)
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ifdef CONFIG_KEXEC
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AFLAGS_kexec_relocate.o := -mcmodel=medany $(call cc-option,-mno-relax)
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endif
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# cmodel=medany and notrace when patching early
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ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
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CFLAGS_alternative.o := -mcmodel=medany
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CFLAGS_cpufeature.o := -mcmodel=medany
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ifdef CONFIG_FTRACE
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CFLAGS_REMOVE_alternative.o = $(CC_FLAGS_FTRACE)
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CFLAGS_REMOVE_cpufeature.o = $(CC_FLAGS_FTRACE)
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endif
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ifdef CONFIG_RELOCATABLE
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CFLAGS_alternative.o += -fno-pie
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CFLAGS_cpufeature.o += -fno-pie
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endif
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ifdef CONFIG_KASAN
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KASAN_SANITIZE_alternative.o := n
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KASAN_SANITIZE_cpufeature.o := n
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endif
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endif
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extra-y += vmlinux.lds
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obj-y += head.o
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obj-y += soc.o
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obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o
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obj-y += cpu.o
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obj-y += cpufeature.o
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obj-y += entry.o
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obj-y += irq.o
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obj-y += process.o
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obj-y += ptrace.o
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obj-y += reset.o
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obj-y += setup.o
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obj-y += signal.o
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obj-y += syscall_table.o
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obj-y += sys_riscv.o
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obj-y += time.o
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obj-y += traps.o
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obj-y += riscv_ksyms.o
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obj-y += stacktrace.o
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obj-y += cacheinfo.o
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obj-y += patch.o
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obj-y += probes/
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obj-$(CONFIG_MMU) += vdso.o vdso/
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obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
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obj-$(CONFIG_FPU) += fpu.o
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obj-$(CONFIG_RISCV_ISA_V) += vector.o
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obj-$(CONFIG_SMP) += smpboot.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SMP) += cpu_ops.o
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obj-$(CONFIG_RISCV_BOOT_SPINWAIT) += cpu_ops_spinwait.o
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obj-$(CONFIG_MODULES) += module.o
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obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
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obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
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obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate-asm.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
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obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
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obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
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obj-$(CONFIG_RISCV_SBI) += sbi.o
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ifeq ($(CONFIG_RISCV_SBI), y)
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obj-$(CONFIG_SMP) += sbi-ipi.o
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obj-$(CONFIG_SMP) += cpu_ops_sbi.o
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endif
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obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o
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obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_KEXEC_CORE) += kexec_relocate.o crash_save_regs.o machine_kexec.o
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obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o machine_kexec_file.o
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obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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obj-$(CONFIG_CRASH_CORE) += crash_core.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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obj-$(CONFIG_EFI) += efi.o
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obj-$(CONFIG_COMPAT) += compat_syscall_table.o
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obj-$(CONFIG_COMPAT) += compat_signal.o
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obj-$(CONFIG_COMPAT) += compat_vdso/
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obj-$(CONFIG_64BIT) += pi/
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obj-$(CONFIG_ACPI) += acpi.o
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