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The HHI register region hosts more than just clocks and needs to accessed drivers other than the clock controller, such as the display driver. This register region should be managed by syscon. It is already the case on gxbb/gxl and it soon will be on axg. The clock controllers must use this system controller instead of directly mapping the registers. This changes the bindings of gxbb and axg's clock controllers. This is due to an initial 'incomplete' knowledge of these SoCs, which is why the meson bindings are unstable ATM. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
46 lines
1.3 KiB
Plaintext
46 lines
1.3 KiB
Plaintext
* Amlogic GXBB Clock and Reset Unit
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The Amlogic GXBB clock controller generates and supplies clock to various
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controllers within the SoC.
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Required Properties:
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- compatible: should be:
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"amlogic,gxbb-clkc" for GXBB SoC,
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
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"amlogic,meson-axg-hhi-sysctrl"
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- reg: base address and size of the HHI system control register space.
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Example: Clock controller node:
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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#clock-cells = <1>;
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compatible = "amlogic,gxbb-clkc";
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};
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart_AO: serial@c81004c0 {
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compatible = "amlogic,meson-uart";
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reg = <0xc81004c0 0x14>;
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interrupts = <0 90 1>;
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clocks = <&clkc CLKID_CLK81>;
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};
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