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The GIC Hypervisor Configuration Register is used to enable the delivery of virtual interupts to a guest, as well as to define in which conditions maintenance interrupts are delivered to the host. This register doesn't contain any information that we need to read back (the EOIcount is utterly useless for us). So let's save ourselves some cycles, and not save it before writing zero to it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
135 lines
3.3 KiB
ArmAsm
135 lines
3.3 KiB
ArmAsm
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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.text
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.pushsection .hyp.text, "ax"
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/*
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* Save the VGIC CPU state into memory
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* x0: Register pointing to VCPU struct
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* Do not corrupt x1!!!
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*/
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ENTRY(__save_vgic_v2_state)
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__save_vgic_v2_state:
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/* Get VGIC VCTRL base into x2 */
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ldr x2, [x0, #VCPU_KVM]
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kern_hyp_va x2
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ldr x2, [x2, #KVM_VGIC_VCTRL]
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kern_hyp_va x2
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cbz x2, 2f // disabled
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/* Compute the address of struct vgic_cpu */
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add x3, x0, #VCPU_VGIC_CPU
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/* Save all interesting registers */
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ldr w5, [x2, #GICH_VMCR]
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ldr w6, [x2, #GICH_MISR]
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ldr w7, [x2, #GICH_EISR0]
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ldr w8, [x2, #GICH_EISR1]
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ldr w9, [x2, #GICH_ELRSR0]
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ldr w10, [x2, #GICH_ELRSR1]
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ldr w11, [x2, #GICH_APR]
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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CPU_BE( rev w7, w7 )
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CPU_BE( rev w8, w8 )
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CPU_BE( rev w9, w9 )
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CPU_BE( rev w10, w10 )
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CPU_BE( rev w11, w11 )
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str w5, [x3, #VGIC_V2_CPU_VMCR]
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str w6, [x3, #VGIC_V2_CPU_MISR]
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CPU_LE( str w7, [x3, #VGIC_V2_CPU_EISR] )
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CPU_LE( str w8, [x3, #(VGIC_V2_CPU_EISR + 4)] )
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CPU_LE( str w9, [x3, #VGIC_V2_CPU_ELRSR] )
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CPU_LE( str w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
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CPU_BE( str w7, [x3, #(VGIC_V2_CPU_EISR + 4)] )
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CPU_BE( str w8, [x3, #VGIC_V2_CPU_EISR] )
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CPU_BE( str w9, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
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CPU_BE( str w10, [x3, #VGIC_V2_CPU_ELRSR] )
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str w11, [x3, #VGIC_V2_CPU_APR]
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/* Clear GICH_HCR */
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str wzr, [x2, #GICH_HCR]
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/* Save list registers */
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add x2, x2, #GICH_LR0
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ldr w4, [x3, #VGIC_CPU_NR_LR]
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add x3, x3, #VGIC_V2_CPU_LR
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1: ldr w5, [x2], #4
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CPU_BE( rev w5, w5 )
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str w5, [x3], #4
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sub w4, w4, #1
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cbnz w4, 1b
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2:
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ret
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ENDPROC(__save_vgic_v2_state)
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/*
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* Restore the VGIC CPU state from memory
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* x0: Register pointing to VCPU struct
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*/
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ENTRY(__restore_vgic_v2_state)
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__restore_vgic_v2_state:
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/* Get VGIC VCTRL base into x2 */
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ldr x2, [x0, #VCPU_KVM]
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kern_hyp_va x2
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ldr x2, [x2, #KVM_VGIC_VCTRL]
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kern_hyp_va x2
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cbz x2, 2f // disabled
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/* Compute the address of struct vgic_cpu */
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add x3, x0, #VCPU_VGIC_CPU
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/* We only restore a minimal set of registers */
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ldr w4, [x3, #VGIC_V2_CPU_HCR]
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ldr w5, [x3, #VGIC_V2_CPU_VMCR]
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ldr w6, [x3, #VGIC_V2_CPU_APR]
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CPU_BE( rev w4, w4 )
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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str w4, [x2, #GICH_HCR]
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str w5, [x2, #GICH_VMCR]
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str w6, [x2, #GICH_APR]
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/* Restore list registers */
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add x2, x2, #GICH_LR0
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ldr w4, [x3, #VGIC_CPU_NR_LR]
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add x3, x3, #VGIC_V2_CPU_LR
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1: ldr w5, [x3], #4
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CPU_BE( rev w5, w5 )
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str w5, [x2], #4
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sub w4, w4, #1
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cbnz w4, 1b
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2:
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ret
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ENDPROC(__restore_vgic_v2_state)
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.popsection
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