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cd6f32aa08
We already had a syscall that did some dcache flushing, but it was not used in practice. Make it MIPS compatible instead so it can do both the DCACHE and ICACHE actions. We have code that wants to be able to use the ICACHE flush mode from userspace so this change enables that. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
48 lines
1.5 KiB
C
48 lines
1.5 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
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#define _ASM_TILE_UNISTD_H
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#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
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/* Use the flavor of this syscall that matches the 32-bit API better. */
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#define __ARCH_WANT_SYNC_FILE_RANGE2
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#endif
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/* Use the standard ABI for syscalls. */
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#include <asm-generic/unistd.h>
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/* Additional Tilera-specific syscalls. */
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#define __NR_cacheflush (__NR_arch_specific_syscall + 1)
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__SYSCALL(__NR_cacheflush, sys_cacheflush)
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#ifndef __tilegx__
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/* "Fast" syscalls provide atomic support for 32-bit chips. */
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#define __NR_FAST_cmpxchg -1
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#define __NR_FAST_atomic_update -2
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#define __NR_FAST_cmpxchg64 -3
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#define __NR_cmpxchg_badaddr (__NR_arch_specific_syscall + 0)
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__SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
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#endif
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#ifdef __KERNEL__
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/* In compat mode, we use sys_llseek() for compat_sys_llseek(). */
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#ifdef CONFIG_COMPAT
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#define __ARCH_WANT_SYS_LLSEEK
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#endif
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#define __ARCH_WANT_SYS_NEWFSTATAT
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#endif
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#endif /* _ASM_TILE_UNISTD_H */
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