mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2025-01-19 20:34:20 +08:00
0e30ca5ab0
The PPU contains a series of identical MMIO register ranges, one for each power domain. Each range contains control/status bits for a clock gate, reset line, output gates, and a power switch. (The clock and reset are separate from, and in addition to, the bits in the CCU.) It also contains a hardware power sequence engine to control the other bits. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20230126063419.15971-3-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
5 lines
163 B
Makefile
5 lines
163 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
|
|
obj-$(CONFIG_SUNXI_MBUS) += sunxi_mbus.o
|
|
obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o
|
|
obj-$(CONFIG_SUN20I_PPU) += sun20i-ppu.o
|