mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-18 17:54:13 +08:00
0eee0fbd41
This patch increases the interleave factor for parallel AES modes to 4x. This improves performance on Cortex-A57 by ~35%. This is due to the 3-cycle latency of AES instructions on the A57's relatively deep pipeline (compared to Cortex-A53 where the AES instruction latency is only 2 cycles). At the same time, disable inline expansion of the core AES functions, as the performance benefit of this feature is negligible. Measured on AMD Seattle (using tcrypt.ko mode=500 sec=1): Baseline (2x interleave, inline expansion) ------------------------------------------ testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 95545 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 68496 operations in 1 seconds This patch (4x interleave, no inline expansion) ----------------------------------------------- testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 124735 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 92328 operations in 1 seconds Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
||
|---|---|---|
| .. | ||
| aes-ce-ccm-core.S | ||
| aes-ce-ccm-glue.c | ||
| aes-ce-cipher.c | ||
| aes-ce-setkey.h | ||
| aes-ce.S | ||
| aes-glue.c | ||
| aes-modes.S | ||
| aes-neon.S | ||
| crc32-arm64.c | ||
| ghash-ce-core.S | ||
| ghash-ce-glue.c | ||
| Kconfig | ||
| Makefile | ||
| sha1-ce-core.S | ||
| sha1-ce-glue.c | ||
| sha2-ce-core.S | ||
| sha2-ce-glue.c | ||