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9b505cf549
An experimental test with the command below gives for example this error: arch/arm/boot/dts/rk3036-evb.dt.yaml: i2s@10220000: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' '#address-cells' and '#size-cells' are not a valid property for i2s nodes, so remove them. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-i2s.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200311162524.19748-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
800 lines
17 KiB
Plaintext
800 lines
17 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include <dt-bindings/power/rk3188-power.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x2>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x3>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE3>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <875000>;
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clock-latency-ns = <40000>;
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <925000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000>;
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opp-suspend;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <975000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1075000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1150000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <1250000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1350000>;
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};
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop0_out>, <&vop1_out>;
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x8000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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vop0: vop@1010c000 {
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compatible = "rockchip,rk3188-vop";
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reg = <0x1010c000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3188_PD_VIO>;
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop0_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vop1: vop@1010e000 {
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compatible = "rockchip,rk3188-vop";
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reg = <0x1010e000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3188_PD_VIO>;
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resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop1_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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timer3: timer@2000e000 {
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compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
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reg = <0x2000e000 0x20>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
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clock-names = "timer", "pclk";
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};
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timer6: timer@200380a0 {
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compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
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reg = <0x200380a0 0x20>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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i2s0: i2s@1011a000 {
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compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
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reg = <0x1011a000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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clock-names = "i2s_clk", "i2s_hclk";
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dmas = <&dmac1_s 6>, <&dmac1_s 7>;
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dma-names = "tx", "rx";
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rockchip,playback-channels = <2>;
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rockchip,capture-channels = <2>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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spdif: sound@1011e000 {
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compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
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reg = <0x1011e000 0x2000>;
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#sound-dai-cells = <0>;
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clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
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clock-names = "mclk", "hclk";
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dmas = <&dmac1_s 8>;
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dma-names = "tx";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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efuse: efuse@20010000 {
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compatible = "rockchip,rk3188-efuse";
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reg = <0x20010000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_EFUSE>;
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clock-names = "pclk_efuse";
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cpu_leakage: cpu_leakage@17 {
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reg = <0x17 0x1>;
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};
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};
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usbphy: phy {
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compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy@10c {
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#phy-cells = <0>;
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reg = <0x10c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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usbphy1: usb-phy@11c {
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#phy-cells = <0>;
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reg = <0x11c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg_pull_up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg_pull_down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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emmc {
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emmc_clk: emmc-clk {
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rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
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};
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emmc_rst: emmc-rst {
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rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
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};
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/*
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* The data pins are shared between nandc and emmc and
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* not accessible through pinctrl. Also they should've
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* been already set correctly by firmware, as
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* flash/emmc is the boot-device.
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*/
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};
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emac {
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emac_xfer: emac-xfer {
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rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
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<3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
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<3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
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<3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
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<3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
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<3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
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<3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
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<3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
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};
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emac_mdio: emac-mdio {
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rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
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<3 RK_PD1 2 &pcfg_pull_none>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
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<1 RK_PD1 1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
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<1 RK_PD3 1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
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<1 RK_PD5 1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
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<3 RK_PB7 2 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
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<1 RK_PD7 1 &pcfg_pull_none>;
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};
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};
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lcdc1 {
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lcdc1_dclk: lcdc1-dclk {
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rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
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};
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lcdc1_den: lcdc1-den {
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rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
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};
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lcdc1_hsync: lcdc1-hsync {
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rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
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};
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lcdc1_vsync: lcdc1-vsync {
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rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
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};
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lcdc1_rgb24: ldcd1-rgb24 {
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rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
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<2 RK_PA1 1 &pcfg_pull_none>,
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<2 RK_PA2 1 &pcfg_pull_none>,
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<2 RK_PA3 1 &pcfg_pull_none>,
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<2 RK_PA4 1 &pcfg_pull_none>,
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<2 RK_PA5 1 &pcfg_pull_none>,
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<2 RK_PA6 1 &pcfg_pull_none>,
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<2 RK_PA7 1 &pcfg_pull_none>,
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<2 RK_PB0 1 &pcfg_pull_none>,
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<2 RK_PB1 1 &pcfg_pull_none>,
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<2 RK_PB2 1 &pcfg_pull_none>,
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<2 RK_PB3 1 &pcfg_pull_none>,
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<2 RK_PB4 1 &pcfg_pull_none>,
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<2 RK_PB5 1 &pcfg_pull_none>,
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<2 RK_PB6 1 &pcfg_pull_none>,
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<2 RK_PB7 1 &pcfg_pull_none>,
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<2 RK_PC0 1 &pcfg_pull_none>,
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<2 RK_PC1 1 &pcfg_pull_none>,
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<2 RK_PC2 1 &pcfg_pull_none>,
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<2 RK_PC3 1 &pcfg_pull_none>,
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<2 RK_PC4 1 &pcfg_pull_none>,
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<2 RK_PC5 1 &pcfg_pull_none>,
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<2 RK_PC6 1 &pcfg_pull_none>,
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<2 RK_PC7 1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_out: pwm0-out {
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rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_out: pwm1-out {
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rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
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};
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};
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pwm2 {
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pwm2_out: pwm2-out {
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rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
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};
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};
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pwm3 {
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pwm3_out: pwm3-out {
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rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
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};
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};
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spi0 {
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spi0_clk: spi0-clk {
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rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
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};
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spi0_cs0: spi0-cs0 {
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rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
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};
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spi0_tx: spi0-tx {
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rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
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};
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spi0_rx: spi0-rx {
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rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
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};
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spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
|
|
<1 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
|
|
<1 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
|
|
<1 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sd0 {
|
|
sd0_clk: sd0-clk {
|
|
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_cmd: sd0-cmd {
|
|
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_cd: sd0-cd {
|
|
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_wp: sd0-wp {
|
|
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_pwr: sd0-pwr {
|
|
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_bus1: sd0-bus-width1 {
|
|
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_bus4: sd0-bus-width4 {
|
|
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
|
|
<3 RK_PA5 1 &pcfg_pull_none>,
|
|
<3 RK_PA6 1 &pcfg_pull_none>,
|
|
<3 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sd1 {
|
|
sd1_clk: sd1-clk {
|
|
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cmd: sd1-cmd {
|
|
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cd: sd1-cd {
|
|
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_wp: sd1-wp {
|
|
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus1: sd1-bus-width1 {
|
|
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus4: sd1-bus-width4 {
|
|
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
|
|
<3 RK_PC2 1 &pcfg_pull_none>,
|
|
<3 RK_PC3 1 &pcfg_pull_none>,
|
|
<3 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_bus: i2s0-bus {
|
|
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
<1 RK_PC2 1 &pcfg_pull_none>,
|
|
<1 RK_PC3 1 &pcfg_pull_none>,
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
<1 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&emac {
|
|
compatible = "rockchip,rk3188-emac";
|
|
};
|
|
|
|
&global_timer {
|
|
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&local_timer {
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
|
};
|
|
|
|
&gpu {
|
|
compatible = "rockchip,rk3188-mali", "arm,mali-400";
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gp",
|
|
"gpmmu",
|
|
"pp0",
|
|
"ppmmu0",
|
|
"pp1",
|
|
"ppmmu1",
|
|
"pp2",
|
|
"ppmmu2",
|
|
"pp3",
|
|
"ppmmu3";
|
|
power-domains = <&power RK3188_PD_GPU>;
|
|
};
|
|
|
|
&i2c0 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
};
|
|
|
|
&i2c1 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
};
|
|
|
|
&i2c2 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
};
|
|
|
|
&i2c3 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
};
|
|
|
|
&i2c4 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
};
|
|
|
|
&pmu {
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3188-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pd_vio@RK3188_PD_VIO {
|
|
reg = <RK3188_PD_VIO>;
|
|
clocks = <&cru ACLK_LCDC0>,
|
|
<&cru ACLK_LCDC1>,
|
|
<&cru DCLK_LCDC0>,
|
|
<&cru DCLK_LCDC1>,
|
|
<&cru HCLK_LCDC0>,
|
|
<&cru HCLK_LCDC1>,
|
|
<&cru SCLK_CIF0>,
|
|
<&cru ACLK_CIF0>,
|
|
<&cru HCLK_CIF0>,
|
|
<&cru ACLK_IPP>,
|
|
<&cru HCLK_IPP>,
|
|
<&cru ACLK_RGA>,
|
|
<&cru HCLK_RGA>;
|
|
pm_qos = <&qos_lcdc0>,
|
|
<&qos_lcdc1>,
|
|
<&qos_cif0>,
|
|
<&qos_ipp>,
|
|
<&qos_rga>;
|
|
};
|
|
|
|
pd_video@RK3188_PD_VIDEO {
|
|
reg = <RK3188_PD_VIDEO>;
|
|
clocks = <&cru ACLK_VDPU>,
|
|
<&cru ACLK_VEPU>,
|
|
<&cru HCLK_VDPU>,
|
|
<&cru HCLK_VEPU>;
|
|
pm_qos = <&qos_vpu>;
|
|
};
|
|
|
|
pd_gpu@RK3188_PD_GPU {
|
|
reg = <RK3188_PD_GPU>;
|
|
clocks = <&cru ACLK_GPU>;
|
|
pm_qos = <&qos_gpu>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pwm0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_out>;
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_out>;
|
|
};
|
|
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_out>;
|
|
};
|
|
|
|
&pwm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_out>;
|
|
};
|
|
|
|
&spi0 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
};
|
|
|
|
&spi1 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
};
|
|
|
|
&uart0 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
};
|
|
|
|
&uart1 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
};
|
|
|
|
&uart2 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
};
|
|
|
|
&uart3 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
|
|
};
|