mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-17 07:54:54 +08:00
69f5689b6b
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
354 lines
10 KiB
Plaintext
354 lines
10 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree Include file for Marvell Armada XP family SoC
|
|
*
|
|
* Copyright (C) 2012 Marvell
|
|
*
|
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
*
|
|
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
|
* common to all Armada XP SoCs.
|
|
*/
|
|
|
|
#include "armada-xp.dtsi"
|
|
|
|
/ {
|
|
model = "Marvell Armada XP MV78460 SoC";
|
|
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
|
|
|
aliases {
|
|
gpio0 = &gpio0;
|
|
gpio1 = &gpio1;
|
|
gpio2 = &gpio2;
|
|
};
|
|
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "marvell,armada-xp-smp";
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "marvell,sheeva-v7";
|
|
reg = <0>;
|
|
clocks = <&cpuclk 0>;
|
|
clock-latency = <1000000>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "marvell,sheeva-v7";
|
|
reg = <1>;
|
|
clocks = <&cpuclk 1>;
|
|
clock-latency = <1000000>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "marvell,sheeva-v7";
|
|
reg = <2>;
|
|
clocks = <&cpuclk 2>;
|
|
clock-latency = <1000000>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "marvell,sheeva-v7";
|
|
reg = <3>;
|
|
clocks = <&cpuclk 3>;
|
|
clock-latency = <1000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
/*
|
|
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
|
* configured as x4 or quad x1 lanes. Two units are
|
|
* x4/x1.
|
|
*/
|
|
pciec: pcie@82000000 {
|
|
compatible = "marvell,armada-xp-pcie";
|
|
status = "disabled";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
msi-parent = <&mpic>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
ranges =
|
|
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
|
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
|
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
|
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
|
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
|
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
|
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
|
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
|
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
|
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
|
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
|
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
|
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
|
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
|
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
|
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
|
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
|
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
|
|
|
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
|
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
|
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
|
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
|
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
|
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
|
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
|
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
|
|
|
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
|
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
|
|
|
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
|
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
|
|
|
pcie1: pcie@1,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 58>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2: pcie@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
|
reg = <0x1000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 59>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <1>;
|
|
clocks = <&gateclk 6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie3: pcie@3,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
|
reg = <0x1800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
|
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 60>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <2>;
|
|
clocks = <&gateclk 7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie4: pcie@4,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
|
reg = <0x2000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
|
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 61>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <3>;
|
|
clocks = <&gateclk 8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie5: pcie@5,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
|
reg = <0x2800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
|
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 62>;
|
|
marvell,pcie-port = <1>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie6: pcie@6,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
|
reg = <0x3000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
|
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 63>;
|
|
marvell,pcie-port = <1>;
|
|
marvell,pcie-lane = <1>;
|
|
clocks = <&gateclk 10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie7: pcie@7,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
|
reg = <0x3800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
|
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 64>;
|
|
marvell,pcie-port = <1>;
|
|
marvell,pcie-lane = <2>;
|
|
clocks = <&gateclk 11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie8: pcie@8,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
|
reg = <0x4000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
|
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 65>;
|
|
marvell,pcie-port = <1>;
|
|
marvell,pcie-lane = <3>;
|
|
clocks = <&gateclk 12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie9: pcie@9,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
|
reg = <0x4800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
|
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 99>;
|
|
marvell,pcie-port = <2>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 26>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie10: pcie@a,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
|
reg = <0x5000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
|
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &mpic 103>;
|
|
marvell,pcie-port = <3>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 27>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
internal-regs {
|
|
gpio0: gpio@18100 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
|
reg-names = "gpio", "pwm";
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <82>, <83>, <84>, <85>;
|
|
clocks = <&coreclk 0>;
|
|
};
|
|
|
|
gpio1: gpio@18140 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
|
reg-names = "gpio", "pwm";
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
#pwm-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <87>, <88>, <89>, <90>;
|
|
clocks = <&coreclk 0>;
|
|
};
|
|
|
|
gpio2: gpio@18180 {
|
|
compatible = "marvell,armada-370-gpio",
|
|
"marvell,orion-gpio";
|
|
reg = <0x18180 0x40>;
|
|
ngpios = <3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <91>;
|
|
};
|
|
|
|
eth3: ethernet@34000 {
|
|
compatible = "marvell,armada-xp-neta";
|
|
reg = <0x34000 0x4000>;
|
|
interrupts = <14>;
|
|
clocks = <&gateclk 1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
compatible = "marvell,mv78460-pinctrl";
|
|
};
|