mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-29 22:14:41 +08:00
518d2f43c3
Modify Nuvoton NPCM7xx device tree structure by adding nuvoton common nNPCM7xx device tree structure that include all common modules. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
45 lines
892 B
Plaintext
45 lines
892 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
|
|
// Copyright 2018 Google, Inc.
|
|
|
|
#include "nuvoton-common-npcm7xx.dtsi"
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "nuvoton,npcm750-smp";
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
clocks = <&clk 0>;
|
|
clock-names = "clk_cpu";
|
|
reg = <0>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
clocks = <&clk 0>;
|
|
clock-names = "clk_cpu";
|
|
reg = <1>;
|
|
next-level-cache = <&l2>;
|
|
};
|
|
};
|
|
soc {
|
|
timer@3fe600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x3fe600 0x20>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
|
IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&clk 5>;
|
|
};
|
|
};
|
|
};
|