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c79e387389
The usual behavior of mask registers is writing a '1' bit to
disable (mask) an interrupt; similarly, writing a '1' bit to
an unmask register enables (unmasks) an interrupt.
Due to a longstanding issue in regmap-irq, mask and unmask
registers were inverted when both kinds of registers were
present on the same chip, ie. regmap-irq actually wrote '1's
to the mask register to enable an IRQ and '1's to the unmask
register to disable an IRQ.
This was fixed by commit e8ffb12e7f ("regmap-irq: Fix
inverted handling of unmask registers") but the fix is opt-in
via mask_unmask_non_inverted = true because it requires manual
changes for each affected driver. The new behavior will become
the default once all drivers have been updated.
The STPMIC1 has a normal mask register with separate set and
clear registers. The driver intends to use the set & clear
registers with regmap-irq and has compensated for regmap-irq's
inverted behavior, and should currently be working properly.
Thus, swap mask_base and unmask_base, and opt in to the new
non-inverted behavior.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-16-aidanmacdonald.0x0@gmail.com
212 lines
6.0 KiB
C
212 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) STMicroelectronics 2018
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// Author: Pascal Paillet <p.paillet@st.com>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/stpmic1.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <dt-bindings/mfd/st,stpmic1.h>
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#define STPMIC1_MAIN_IRQ 0
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static const struct regmap_range stpmic1_readable_ranges[] = {
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regmap_reg_range(TURN_ON_SR, VERSION_SR),
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regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
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regmap_reg_range(BST_SW_CR, BST_SW_CR),
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regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
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regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
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regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
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regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
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regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
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regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
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};
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static const struct regmap_range stpmic1_writeable_ranges[] = {
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regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
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regmap_reg_range(BST_SW_CR, BST_SW_CR),
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regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
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regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
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regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
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};
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static const struct regmap_range stpmic1_volatile_ranges[] = {
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regmap_reg_range(TURN_ON_SR, VERSION_SR),
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regmap_reg_range(WCHDG_CR, WCHDG_CR),
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regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
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regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
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};
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static const struct regmap_access_table stpmic1_readable_table = {
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.yes_ranges = stpmic1_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
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};
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static const struct regmap_access_table stpmic1_writeable_table = {
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.yes_ranges = stpmic1_writeable_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
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};
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static const struct regmap_access_table stpmic1_volatile_table = {
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.yes_ranges = stpmic1_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
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};
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static const struct regmap_config stpmic1_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.max_register = PMIC_MAX_REGISTER_ADDRESS,
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.rd_table = &stpmic1_readable_table,
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.wr_table = &stpmic1_writeable_table,
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.volatile_table = &stpmic1_volatile_table,
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};
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static const struct regmap_irq stpmic1_irqs[] = {
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REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
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REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
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REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
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REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
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REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
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REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
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REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
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REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
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REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
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REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
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REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
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REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
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REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
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REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
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REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
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REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
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REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
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REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
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REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
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REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
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REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
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REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
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REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
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REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
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REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
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REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
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};
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static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
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.name = "pmic_irq",
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.status_base = INT_PENDING_R1,
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.mask_base = INT_SET_MASK_R1,
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.unmask_base = INT_CLEAR_MASK_R1,
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.mask_unmask_non_inverted = true,
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.ack_base = INT_CLEAR_R1,
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.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
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.irqs = stpmic1_irqs,
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.num_irqs = ARRAY_SIZE(stpmic1_irqs),
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};
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static int stpmic1_probe(struct i2c_client *i2c)
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{
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struct stpmic1 *ddata;
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struct device *dev = &i2c->dev;
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int ret;
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struct device_node *np = dev->of_node;
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u32 reg;
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ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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i2c_set_clientdata(i2c, ddata);
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ddata->dev = dev;
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ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
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if (IS_ERR(ddata->regmap))
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return PTR_ERR(ddata->regmap);
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ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
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if (ddata->irq < 0) {
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dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
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return ddata->irq;
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}
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ret = regmap_read(ddata->regmap, VERSION_SR, ®);
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if (ret) {
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dev_err(dev, "Unable to read PMIC version\n");
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return ret;
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}
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dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
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/* Initialize PMIC IRQ Chip & associated IRQ domains */
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ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
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IRQF_ONESHOT | IRQF_SHARED,
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0, &stpmic1_regmap_irq_chip,
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&ddata->irq_data);
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if (ret) {
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dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
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return ret;
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}
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return devm_of_platform_populate(dev);
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}
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static int stpmic1_suspend(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
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disable_irq(pmic_dev->irq);
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return 0;
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}
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static int stpmic1_resume(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
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int ret;
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ret = regcache_sync(pmic_dev->regmap);
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if (ret)
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return ret;
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enable_irq(pmic_dev->irq);
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
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static const struct of_device_id stpmic1_of_match[] = {
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{ .compatible = "st,stpmic1", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stpmic1_of_match);
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static struct i2c_driver stpmic1_driver = {
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.driver = {
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.name = "stpmic1",
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.of_match_table = of_match_ptr(stpmic1_of_match),
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.pm = pm_sleep_ptr(&stpmic1_pm),
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},
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.probe_new = stpmic1_probe,
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};
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module_i2c_driver(stpmic1_driver);
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MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
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MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
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MODULE_LICENSE("GPL v2");
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