Ben Widawsky ba26864736 cxl/component_regs: Fix offset ... The CXL.cache and CXL.mem registers begin after the CXL.io registers which occupy the first 0x1000 bytes. The current code wasn't setting this up properly for future users of the component registers. It was correct for the probing code however. Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Ira Weiny <ira.weiny@intel.com> Fixes: 08422378c4 ("cxl/pci: Add HDM decoder capabilities") Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20210611051113.224328-1-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2021-06-12 10:30:41 -07:00
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acpi.c	cxl/acpi: Introduce cxl_decoder objects	2021-06-09 18:02:39 -07:00
core.c	cxl/component_regs: Fix offset	2021-06-12 10:30:41 -07:00
cxl.h	cxl/hdm: Fix decoder count calculation	2021-06-12 10:29:03 -07:00
Kconfig	cxl/Kconfig: Default drivers to CONFIG_CXL_BUS	2021-06-09 18:02:38 -07:00
Makefile	cxl/acpi: Introduce the root of a cxl_port topology	2021-06-09 18:02:38 -07:00
mem.h	cxl/mem: Get rid of @cxlm.base	2021-05-26 11:20:18 -07:00
pci.c	cxl/pci: Add HDM decoder capabilities	2021-06-05 17:39:12 -07:00
pci.h	cxl/mem: Find device capabilities	2021-02-16 20:36:38 -08:00