Dan Williams b9cc98697d ioat3: interrupt coalescing ... The hardware automatically disables further interrupts after each event until rearmed. This allows a delay to be injected between the occurence of the interrupt and the running of the cleanup routine. The delay is scaled by the descriptor backlog and then written to the INTRDELAY register which specifies the number of microseconds to hold off interrupt delivery after an interrupt event occurs. According to powertop this reduces the interrupt rate from ~5000 intr/s to ~150 intr/s per without affecting throughput (simple dd to a raid6 array). Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2010-03-03 21:21:13 -07:00
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dca.c	ioat3: dca and raid operations are incompatible	2009-11-19 17:07:10 -07:00
dma_v2.c	ioat: close potential BUG_ON race in the descriptor cleanup path	2010-03-03 21:21:10 -07:00
dma_v2.h	ioat2: kill pending flag	2010-03-03 11:47:43 -07:00
dma_v3.c	ioat3: interrupt coalescing	2010-03-03 21:21:13 -07:00
dma.c	ioat2,3: put channel hardware in known state at init	2009-12-19 15:36:02 -07:00
dma.h	ioat2,3: put channel hardware in known state at init	2009-12-19 15:36:02 -07:00
hw.h	ioat3: dca and raid operations are incompatible	2009-11-19 17:07:10 -07:00
Makefile	ioat3: split ioat3 support to its own file, add memset	2009-09-08 17:42:55 -07:00
pci.c	dca: registering requesters in multiple dca domains	2009-09-10 10:00:05 -07:00
registers.h	ioat3: interrupt coalescing	2010-03-03 21:21:13 -07:00