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The driver is separated by functional parts. The core part implements a platform driver probe and remove callbaks. The probe enables clocks, checks crypto version, initialize and request dma channels, create done tasklet and init crypto queue and finally register the algorithms into crypto core subsystem. - DMA and SG helper functions implement dmaengine and sg-list helper functions used by other parts of the crypto driver. - ablkcipher algorithms implementation of AES, DES and 3DES crypto API callbacks, the crypto register alg function, the async request handler and its dma done callback function. - SHA and HMAC transforms implementation and registration of ahash crypto type. It includes sha1, sha256, hmac(sha1) and hmac(sha256). - infrastructure to setup the crypto hw contains functions used to setup/prepare hardware registers for all algorithms supported by the crypto block. It also exports few helper functions needed by algorithms: - to check hardware status - to start crypto hardware - to translate data stream to big endian form Adds register addresses and bit/masks used by the driver as well. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
187 lines
4.1 KiB
C
187 lines
4.1 KiB
C
/*
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/dmaengine.h>
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#include <crypto/scatterwalk.h>
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#include "dma.h"
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int qce_dma_request(struct device *dev, struct qce_dma_data *dma)
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{
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int ret;
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dma->txchan = dma_request_slave_channel_reason(dev, "tx");
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if (IS_ERR(dma->txchan))
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return PTR_ERR(dma->txchan);
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dma->rxchan = dma_request_slave_channel_reason(dev, "rx");
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if (IS_ERR(dma->rxchan)) {
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ret = PTR_ERR(dma->rxchan);
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goto error_rx;
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}
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dma->result_buf = kmalloc(QCE_RESULT_BUF_SZ + QCE_IGNORE_BUF_SZ,
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GFP_KERNEL);
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if (!dma->result_buf) {
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ret = -ENOMEM;
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goto error_nomem;
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}
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dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ;
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return 0;
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error_nomem:
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dma_release_channel(dma->rxchan);
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error_rx:
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dma_release_channel(dma->txchan);
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return ret;
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}
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void qce_dma_release(struct qce_dma_data *dma)
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{
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dma_release_channel(dma->txchan);
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dma_release_channel(dma->rxchan);
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kfree(dma->result_buf);
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}
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int qce_mapsg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, bool chained)
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{
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int err;
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if (chained) {
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while (sg) {
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err = dma_map_sg(dev, sg, 1, dir);
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if (!err)
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return -EFAULT;
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sg = scatterwalk_sg_next(sg);
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}
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} else {
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err = dma_map_sg(dev, sg, nents, dir);
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if (!err)
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return -EFAULT;
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}
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return nents;
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}
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void qce_unmapsg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, bool chained)
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{
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if (chained)
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while (sg) {
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dma_unmap_sg(dev, sg, 1, dir);
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sg = scatterwalk_sg_next(sg);
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}
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else
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dma_unmap_sg(dev, sg, nents, dir);
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}
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int qce_countsg(struct scatterlist *sglist, int nbytes, bool *chained)
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{
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struct scatterlist *sg = sglist;
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int nents = 0;
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if (chained)
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*chained = false;
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while (nbytes > 0 && sg) {
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nents++;
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nbytes -= sg->length;
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if (!sg_is_last(sg) && (sg + 1)->length == 0 && chained)
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*chained = true;
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sg = scatterwalk_sg_next(sg);
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}
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return nents;
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}
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struct scatterlist *
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qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl)
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{
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struct scatterlist *sg = sgt->sgl, *sg_last = NULL;
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while (sg) {
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if (!sg_page(sg))
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break;
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sg = sg_next(sg);
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}
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if (!sg)
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return ERR_PTR(-EINVAL);
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while (new_sgl && sg) {
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sg_set_page(sg, sg_page(new_sgl), new_sgl->length,
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new_sgl->offset);
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sg_last = sg;
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sg = sg_next(sg);
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new_sgl = sg_next(new_sgl);
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}
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return sg_last;
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}
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static int qce_dma_prep_sg(struct dma_chan *chan, struct scatterlist *sg,
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int nents, unsigned long flags,
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enum dma_transfer_direction dir,
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dma_async_tx_callback cb, void *cb_param)
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{
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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if (!sg || !nents)
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return -EINVAL;
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desc = dmaengine_prep_slave_sg(chan, sg, nents, dir, flags);
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if (!desc)
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return -EINVAL;
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desc->callback = cb;
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desc->callback_param = cb_param;
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cookie = dmaengine_submit(desc);
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return dma_submit_error(cookie);
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}
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int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *rx_sg,
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int rx_nents, struct scatterlist *tx_sg, int tx_nents,
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dma_async_tx_callback cb, void *cb_param)
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{
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struct dma_chan *rxchan = dma->rxchan;
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struct dma_chan *txchan = dma->txchan;
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
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int ret;
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ret = qce_dma_prep_sg(rxchan, rx_sg, rx_nents, flags, DMA_MEM_TO_DEV,
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NULL, NULL);
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if (ret)
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return ret;
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return qce_dma_prep_sg(txchan, tx_sg, tx_nents, flags, DMA_DEV_TO_MEM,
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cb, cb_param);
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}
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void qce_dma_issue_pending(struct qce_dma_data *dma)
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{
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dma_async_issue_pending(dma->rxchan);
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dma_async_issue_pending(dma->txchan);
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}
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int qce_dma_terminate_all(struct qce_dma_data *dma)
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{
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int ret;
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ret = dmaengine_terminate_all(dma->rxchan);
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return ret ?: dmaengine_terminate_all(dma->txchan);
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}
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