mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-19 00:54:41 +08:00
d82ca49f3e
Add a binding for an extra clock required on i.MX8MQ. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org
98 lines
3.8 KiB
Plaintext
98 lines
3.8 KiB
Plaintext
* Freescale i.MX6 PCIe interface
|
|
|
|
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
|
and thus inherits all the common properties defined in designware-pcie.txt.
|
|
|
|
Required properties:
|
|
- compatible:
|
|
- "fsl,imx6q-pcie"
|
|
- "fsl,imx6sx-pcie",
|
|
- "fsl,imx6qp-pcie"
|
|
- "fsl,imx7d-pcie"
|
|
- "fsl,imx8mq-pcie"
|
|
- reg: base address and length of the PCIe controller
|
|
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
|
entry for each entry in the interrupt-names property.
|
|
- interrupt-names: Must include the following entries:
|
|
- "msi": The interrupt that is asserted when an MSI is received
|
|
- clock-names: Must include the following additional entries:
|
|
- "pcie_phy"
|
|
|
|
Optional properties:
|
|
- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
|
|
- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
|
|
- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
|
|
- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
|
|
- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
|
|
- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
|
|
gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
|
|
do not meet gen2 jitter requirements and thus for gen2 capability a gen2
|
|
compliant clock generator should be used and configured.
|
|
- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
|
|
signal. It's not polarity aware and defaults to active-low reset sequence
|
|
(L=reset state, H=operation state).
|
|
- reset-gpio-active-high: If present then the reset sequence using the GPIO
|
|
specified in the "reset-gpio" property is reversed (H=reset state,
|
|
L=operation state).
|
|
- vpcie-supply: Should specify the regulator in charge of PCIe port power.
|
|
The regulator will be enabled when initializing the PCIe host and
|
|
disabled either as part of the init process or when shutting down the
|
|
host.
|
|
|
|
Additional required properties for imx6sx-pcie:
|
|
- clock names: Must include the following additional entries:
|
|
- "pcie_inbound_axi"
|
|
- power-domains: Must be set to phandles pointing to the DISPLAY and
|
|
PCIE_PHY power domains
|
|
- power-domain-names: Must be "pcie", "pcie_phy"
|
|
|
|
Additional required properties for imx7d-pcie and imx8mq-pcie:
|
|
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
|
|
- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
|
|
IP block
|
|
- reset-names: Must contain the following entires:
|
|
- "pciephy"
|
|
- "apps"
|
|
- "turnoff"
|
|
- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
|
|
|
|
Additional required properties for imx8mq-pcie:
|
|
- clock-names: Must include the following additional entries:
|
|
- "pcie_aux"
|
|
|
|
Example:
|
|
|
|
pcie@01000000 {
|
|
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
|
|
reg = <0x01ffc000 0x04000>,
|
|
<0x01f00000 0x80000>;
|
|
reg-names = "dbi", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
|
|
0x81000000 0 0 0x01f80000 0 0x00010000
|
|
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
|
|
num-lanes = <1>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 144>, <&clks 206>, <&clks 189>;
|
|
clock-names = "pcie", "pcie_bus", "pcie_phy";
|
|
};
|
|
|
|
* Freescale i.MX7d PCIe PHY
|
|
|
|
This is the PHY associated with the IMX7d PCIe controller. It's used by the
|
|
PCI-e controller via the fsl,imx7d-pcie-phy phandle.
|
|
|
|
Required properties:
|
|
- compatible:
|
|
- "fsl,imx7d-pcie-phy"
|
|
- reg: base address and length of the PCIe PHY controller
|