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c372257758
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/panel/panel-sitronix-st7701.c:42: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210602143300.2330146-22-lee.jones@linaro.org Link: https://patchwork.freedesktop.org/patch/msgid/20210602143300.2330146-23-lee.jones@linaro.org
419 lines
12 KiB
C
419 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#include <linux/gpio/consumer.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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/* Command2 BKx selection command */
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#define DSI_CMD2BKX_SEL 0xFF
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/* Command2, BK0 commands */
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#define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
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#define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
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#define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
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#define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
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#define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
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/* Command2, BK1 commands */
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#define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
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#define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
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#define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
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#define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
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#define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
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#define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
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#define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
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#define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
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#define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
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#define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
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/*
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* Command2 with BK function selection.
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*
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* BIT[4, 0]: [CN2, BKXSEL]
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* 10 = CMD2BK0, Command2 BK0
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* 11 = CMD2BK1, Command2 BK1
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* 00 = Command2 disable
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*/
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#define DSI_CMD2BK1_SEL 0x11
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#define DSI_CMD2BK0_SEL 0x10
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#define DSI_CMD2BKX_SEL_NONE 0x00
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/* Command2, BK0 bytes */
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#define DSI_LINESET_LINE 0x69
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#define DSI_LINESET_LDE_EN BIT(7)
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#define DSI_LINESET_LINEDELTA GENMASK(1, 0)
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#define DSI_CMD2_BK0_LNESET_B1 DSI_LINESET_LINEDELTA
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#define DSI_CMD2_BK0_LNESET_B0 (DSI_LINESET_LDE_EN | DSI_LINESET_LINE)
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#define DSI_INVSEL_DEFAULT GENMASK(5, 4)
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#define DSI_INVSEL_NLINV GENMASK(2, 0)
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#define DSI_INVSEL_RTNI GENMASK(2, 1)
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#define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI
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#define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV)
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#define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end)
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#define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay)
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/* Command2, BK1 bytes */
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#define DSI_CMD2_BK1_VRHA_SET 0x45
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#define DSI_CMD2_BK1_VCOM_SET 0x13
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#define DSI_CMD2_BK1_VGHSS_SET GENMASK(2, 0)
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#define DSI_CMD2_BK1_TESTCMD_VAL BIT(7)
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#define DSI_VGLS_DEFAULT BIT(6)
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#define DSI_VGLS_SEL GENMASK(2, 0)
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#define DSI_CMD2_BK1_VGLS_SET (DSI_VGLS_DEFAULT | DSI_VGLS_SEL)
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#define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */
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#define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */
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#define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */
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#define DSI_CMD2_BK1_PWCTLR1_SET (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \
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DSI_PWCTLR1_APOS)
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#define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */
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#define DSI_PWCTLR2_AVCL 0x0 /* AVCL -4.4v */
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#define DSI_CMD2_BK1_PWCTLR2_SET (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL)
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#define DSI_SPD1_T2D BIT(3)
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#define DSI_CMD2_BK1_SPD1_SET (GENMASK(6, 4) | DSI_SPD1_T2D)
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#define DSI_CMD2_BK1_SPD2_SET DSI_CMD2_BK1_SPD1_SET
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#define DSI_MIPISET1_EOT_EN BIT(3)
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#define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN)
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struct st7701_panel_desc {
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const struct drm_display_mode *mode;
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unsigned int lanes;
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unsigned long flags;
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enum mipi_dsi_pixel_format format;
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const char *const *supply_names;
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unsigned int num_supplies;
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unsigned int panel_sleep_delay;
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};
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struct st7701 {
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struct drm_panel panel;
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struct mipi_dsi_device *dsi;
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const struct st7701_panel_desc *desc;
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struct regulator_bulk_data *supplies;
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struct gpio_desc *reset;
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unsigned int sleep_delay;
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};
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static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
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{
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return container_of(panel, struct st7701, panel);
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}
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static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
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size_t len)
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{
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return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
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}
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#define ST7701_DSI(st7701, seq...) \
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{ \
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const u8 d[] = { seq }; \
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st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
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}
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static void st7701_init_sequence(struct st7701 *st7701)
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{
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const struct drm_display_mode *mode = st7701->desc->mode;
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ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
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/* We need to wait 5ms before sending new commands */
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msleep(5);
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ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
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msleep(st7701->sleep_delay);
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/* Command2, BK0 */
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ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
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0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);
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ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,
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0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,
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0x2B, 0x34, 0x1F);
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ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,
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0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,
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0x2C, 0x34, 0x1F);
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ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
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DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
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ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
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DSI_CMD2_BK0_PORCTRL_B0(mode),
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DSI_CMD2_BK0_PORCTRL_B1(mode));
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ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
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DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1);
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/* Command2, BK1 */
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ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
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0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL);
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ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
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ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET);
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ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET);
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/**
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* ST7701_SPEC_V1.2 is unable to provide enough information above this
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* specific command sequence, so grab the same from vendor BSP driver.
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*/
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ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
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ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
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0x00, 0x00, 0x44, 0x44);
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ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
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0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
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ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
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ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
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ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
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0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
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ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
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ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
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ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
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0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
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ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
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ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
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ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
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0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
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/* disable Command2 */
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ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
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0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
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}
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static int st7701_prepare(struct drm_panel *panel)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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int ret;
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gpiod_set_value(st7701->reset, 0);
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ret = regulator_bulk_enable(st7701->desc->num_supplies,
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st7701->supplies);
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if (ret < 0)
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return ret;
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msleep(20);
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gpiod_set_value(st7701->reset, 1);
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msleep(150);
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st7701_init_sequence(st7701);
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return 0;
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}
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static int st7701_enable(struct drm_panel *panel)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
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return 0;
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}
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static int st7701_disable(struct drm_panel *panel)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
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return 0;
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}
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static int st7701_unprepare(struct drm_panel *panel)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
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msleep(st7701->sleep_delay);
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gpiod_set_value(st7701->reset, 0);
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/**
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* During the Resetting period, the display will be blanked
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* (The display is entering blanking sequence, which maximum
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* time is 120 ms, when Reset Starts in Sleep Out –mode. The
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* display remains the blank state in Sleep In –mode.) and
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* then return to Default condition for Hardware Reset.
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*
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* So we need wait sleep_delay time to make sure reset completed.
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*/
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msleep(st7701->sleep_delay);
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regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies);
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return 0;
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}
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static int st7701_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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const struct drm_display_mode *desc_mode = st7701->desc->mode;
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, desc_mode);
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if (!mode) {
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dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
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desc_mode->hdisplay, desc_mode->vdisplay,
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drm_mode_vrefresh(desc_mode));
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return -ENOMEM;
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}
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drm_mode_set_name(mode);
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drm_mode_probed_add(connector, mode);
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connector->display_info.width_mm = desc_mode->width_mm;
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connector->display_info.height_mm = desc_mode->height_mm;
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return 1;
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}
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static const struct drm_panel_funcs st7701_funcs = {
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.disable = st7701_disable,
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.unprepare = st7701_unprepare,
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.prepare = st7701_prepare,
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.enable = st7701_enable,
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.get_modes = st7701_get_modes,
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};
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static const struct drm_display_mode ts8550b_mode = {
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.clock = 27500,
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.hdisplay = 480,
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.hsync_start = 480 + 38,
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.hsync_end = 480 + 38 + 12,
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.htotal = 480 + 38 + 12 + 12,
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.vdisplay = 854,
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.vsync_start = 854 + 18,
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.vsync_end = 854 + 18 + 8,
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.vtotal = 854 + 18 + 8 + 4,
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.width_mm = 69,
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.height_mm = 139,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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};
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static const char * const ts8550b_supply_names[] = {
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"VCC",
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"IOVCC",
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};
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static const struct st7701_panel_desc ts8550b_desc = {
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.mode = &ts8550b_mode,
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.lanes = 2,
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.flags = MIPI_DSI_MODE_VIDEO,
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.format = MIPI_DSI_FMT_RGB888,
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.supply_names = ts8550b_supply_names,
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.num_supplies = ARRAY_SIZE(ts8550b_supply_names),
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.panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
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};
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static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
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{
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const struct st7701_panel_desc *desc;
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struct st7701 *st7701;
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int ret, i;
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st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL);
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if (!st7701)
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return -ENOMEM;
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desc = of_device_get_match_data(&dsi->dev);
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dsi->mode_flags = desc->flags;
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dsi->format = desc->format;
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dsi->lanes = desc->lanes;
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st7701->supplies = devm_kcalloc(&dsi->dev, desc->num_supplies,
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sizeof(*st7701->supplies),
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GFP_KERNEL);
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if (!st7701->supplies)
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return -ENOMEM;
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for (i = 0; i < desc->num_supplies; i++)
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st7701->supplies[i].supply = desc->supply_names[i];
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ret = devm_regulator_bulk_get(&dsi->dev, desc->num_supplies,
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st7701->supplies);
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if (ret < 0)
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return ret;
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st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(st7701->reset)) {
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dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
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return PTR_ERR(st7701->reset);
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}
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drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
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DRM_MODE_CONNECTOR_DSI);
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/**
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* Once sleep out has been issued, ST7701 IC required to wait 120ms
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* before initiating new commands.
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*
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* On top of that some panels might need an extra delay to wait, so
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* add panel specific delay for those cases. As now this panel specific
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* delay information is referenced from those panel BSP driver, example
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* ts8550b and there is no valid documentation for that.
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*/
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st7701->sleep_delay = 120 + desc->panel_sleep_delay;
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ret = drm_panel_of_backlight(&st7701->panel);
|
||
if (ret)
|
||
return ret;
|
||
|
||
drm_panel_add(&st7701->panel);
|
||
|
||
mipi_dsi_set_drvdata(dsi, st7701);
|
||
st7701->dsi = dsi;
|
||
st7701->desc = desc;
|
||
|
||
return mipi_dsi_attach(dsi);
|
||
}
|
||
|
||
static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
|
||
{
|
||
struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
|
||
|
||
mipi_dsi_detach(dsi);
|
||
drm_panel_remove(&st7701->panel);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static const struct of_device_id st7701_of_match[] = {
|
||
{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
|
||
{ }
|
||
};
|
||
MODULE_DEVICE_TABLE(of, st7701_of_match);
|
||
|
||
static struct mipi_dsi_driver st7701_dsi_driver = {
|
||
.probe = st7701_dsi_probe,
|
||
.remove = st7701_dsi_remove,
|
||
.driver = {
|
||
.name = "st7701",
|
||
.of_match_table = st7701_of_match,
|
||
},
|
||
};
|
||
module_mipi_dsi_driver(st7701_dsi_driver);
|
||
|
||
MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
|
||
MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
|
||
MODULE_LICENSE("GPL");
|