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cc51e5428e
On Nehalem and newer core CPUs the CPU cache internally uses 44 bits
physical address space. The L1TF workaround is limited by this internal
cache address width, and needs to have one bit free there for the
mitigation to work.
Older client systems report only 36bit physical address space so the range
check decides that L1TF is not mitigated for a 36bit phys/32GB system with
some memory holes.
But since these actually have the larger internal cache width this warning
is bogus because it would only really be needed if the system had more than
43bits of memory.
Add a new internal x86_cache_bits field. Normally it is the same as the
physical bits field reported by CPUID, but for Nehalem and newerforce it to
be at least 44bits.
Change the L1TF memory size warning to use the new cache_bits field to
avoid bogus warnings and remove the bogus comment about memory size.
Fixes: 17dbca1193
("x86/speculation/l1tf: Add sysfs reporting for l1tf")
Reported-by: George Anchev <studio@anchev.net>
Reported-by: Christopher Snowhill <kode54@gmail.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Michael Hocko <mhocko@suse.com>
Cc: vbabka@suse.cz
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20180824170351.34874-1-andi@firstfloor.org
878 lines
25 KiB
C
878 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Cyrix stuff, June 1998 by:
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* - Rafael R. Reilova (moved everything from head.S),
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* <rreilova@ececs.uc.edu>
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* - Channing Corn (tests & fixes),
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* - Andrew D. Balsa (code cleanup).
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*/
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#include <linux/init.h>
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#include <linux/utsname.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/nospec.h>
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#include <linux/prctl.h>
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#include <asm/spec-ctrl.h>
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#include <asm/cmdline.h>
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#include <asm/bugs.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/fpu/internal.h>
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#include <asm/msr.h>
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#include <asm/vmx.h>
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#include <asm/paravirt.h>
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#include <asm/alternative.h>
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#include <asm/pgtable.h>
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#include <asm/set_memory.h>
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#include <asm/intel-family.h>
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#include <asm/e820/api.h>
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#include <asm/hypervisor.h>
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static void __init spectre_v2_select_mitigation(void);
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static void __init ssb_select_mitigation(void);
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static void __init l1tf_select_mitigation(void);
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/*
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* Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
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* writes to SPEC_CTRL contain whatever reserved bits have been set.
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*/
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u64 __ro_after_init x86_spec_ctrl_base;
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
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/*
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* The vendor and possibly platform specific bits which can be modified in
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* x86_spec_ctrl_base.
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*/
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static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
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/*
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* AMD specific MSR info for Speculative Store Bypass control.
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* x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
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*/
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u64 __ro_after_init x86_amd_ls_cfg_base;
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u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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/*
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* identify_boot_cpu() initialized SMT support information, let the
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* core code know.
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*/
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cpu_smt_check_topology_early();
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if (!IS_ENABLED(CONFIG_SMP)) {
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pr_info("CPU: ");
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print_cpu_info(&boot_cpu_data);
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}
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/*
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* Read the SPEC_CTRL MSR to account for reserved bits which may
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* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
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* init code as it is not enumerated and depends on the family.
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*/
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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/* Allow STIBP in MSR_SPEC_CTRL if supported */
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if (boot_cpu_has(X86_FEATURE_STIBP))
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x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
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/* Select the proper spectre mitigation before patching alternatives */
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spectre_v2_select_mitigation();
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/*
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* Select proper mitigation for any exposure to the Speculative Store
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* Bypass vulnerability.
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*/
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ssb_select_mitigation();
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l1tf_select_mitigation();
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#ifdef CONFIG_X86_32
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/*
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* Check whether we are able to run this kernel safely on SMP.
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*
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* - i386 is no longer supported.
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* - In order to run on anything without a TSC, we need to be
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* compiled for a i486.
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*/
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if (boot_cpu_data.x86 < 4)
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panic("Kernel requires i486+ for 'invlpg' and other features");
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init_utsname()->machine[1] =
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'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
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alternative_instructions();
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fpu__init_check_bugs();
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#else /* CONFIG_X86_64 */
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alternative_instructions();
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/*
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* Make sure the first 2MB area is not mapped by huge pages
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* There are typically fixed size MTRRs in there and overlapping
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* MTRRs into large pages causes slow downs.
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*
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* Right now we don't do that with gbpages because there seems
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* very little benefit for that case.
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*/
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if (!direct_gbpages)
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set_memory_4k((unsigned long)__va(0), 1);
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#endif
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}
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/* The kernel command line selection */
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enum spectre_v2_mitigation_cmd {
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SPECTRE_V2_CMD_NONE,
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SPECTRE_V2_CMD_AUTO,
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SPECTRE_V2_CMD_FORCE,
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SPECTRE_V2_CMD_RETPOLINE,
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SPECTRE_V2_CMD_RETPOLINE_GENERIC,
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SPECTRE_V2_CMD_RETPOLINE_AMD,
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};
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static const char *spectre_v2_strings[] = {
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[SPECTRE_V2_NONE] = "Vulnerable",
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[SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline",
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[SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline",
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[SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
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[SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
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[SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
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};
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#undef pr_fmt
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#define pr_fmt(fmt) "Spectre V2 : " fmt
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static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
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SPECTRE_V2_NONE;
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void
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x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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{
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u64 msrval, guestval, hostval = x86_spec_ctrl_base;
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struct thread_info *ti = current_thread_info();
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/* Is MSR_SPEC_CTRL implemented ? */
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if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
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/*
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* Restrict guest_spec_ctrl to supported values. Clear the
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* modifiable bits in the host base value and or the
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* modifiable bits from the guest value.
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*/
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guestval = hostval & ~x86_spec_ctrl_mask;
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guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
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/* SSBD controlled in MSR_SPEC_CTRL */
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if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
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static_cpu_has(X86_FEATURE_AMD_SSBD))
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hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
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if (hostval != guestval) {
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msrval = setguest ? guestval : hostval;
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wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
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}
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}
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/*
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* If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
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* MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
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*/
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if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
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!static_cpu_has(X86_FEATURE_VIRT_SSBD))
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return;
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/*
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* If the host has SSBD mitigation enabled, force it in the host's
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* virtual MSR value. If its not permanently enabled, evaluate
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* current's TIF_SSBD thread flag.
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*/
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if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
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hostval = SPEC_CTRL_SSBD;
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else
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hostval = ssbd_tif_to_spec_ctrl(ti->flags);
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/* Sanitize the guest value */
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guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
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if (hostval != guestval) {
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unsigned long tif;
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tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
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ssbd_spec_ctrl_to_tif(hostval);
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speculative_store_bypass_update(tif);
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}
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}
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EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
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static void x86_amd_ssb_disable(void)
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{
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u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
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if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
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wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
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else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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wrmsrl(MSR_AMD64_LS_CFG, msrval);
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}
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#ifdef RETPOLINE
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static bool spectre_v2_bad_module;
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bool retpoline_module_ok(bool has_retpoline)
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{
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if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
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return true;
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pr_err("System may be vulnerable to spectre v2\n");
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spectre_v2_bad_module = true;
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return false;
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}
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static inline const char *spectre_v2_module_string(void)
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{
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return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
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}
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#else
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static inline const char *spectre_v2_module_string(void) { return ""; }
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#endif
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static void __init spec2_print_if_insecure(const char *reason)
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{
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if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
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pr_info("%s selected on command line.\n", reason);
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}
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static void __init spec2_print_if_secure(const char *reason)
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{
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if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
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pr_info("%s selected on command line.\n", reason);
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}
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static inline bool retp_compiler(void)
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{
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return __is_defined(RETPOLINE);
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}
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static inline bool match_option(const char *arg, int arglen, const char *opt)
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{
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int len = strlen(opt);
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return len == arglen && !strncmp(arg, opt, len);
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}
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static const struct {
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const char *option;
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enum spectre_v2_mitigation_cmd cmd;
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bool secure;
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} mitigation_options[] = {
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{ "off", SPECTRE_V2_CMD_NONE, false },
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{ "on", SPECTRE_V2_CMD_FORCE, true },
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{ "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
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{ "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
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{ "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
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{ "auto", SPECTRE_V2_CMD_AUTO, false },
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};
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static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
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{
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char arg[20];
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int ret, i;
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enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
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if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
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return SPECTRE_V2_CMD_NONE;
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else {
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ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
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if (ret < 0)
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return SPECTRE_V2_CMD_AUTO;
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for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
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if (!match_option(arg, ret, mitigation_options[i].option))
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continue;
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cmd = mitigation_options[i].cmd;
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break;
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}
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if (i >= ARRAY_SIZE(mitigation_options)) {
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pr_err("unknown option (%s). Switching to AUTO select\n", arg);
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return SPECTRE_V2_CMD_AUTO;
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}
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}
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if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
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cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
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cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
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!IS_ENABLED(CONFIG_RETPOLINE)) {
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pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
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return SPECTRE_V2_CMD_AUTO;
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}
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if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
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boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
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pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
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return SPECTRE_V2_CMD_AUTO;
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}
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if (mitigation_options[i].secure)
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spec2_print_if_secure(mitigation_options[i].option);
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else
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spec2_print_if_insecure(mitigation_options[i].option);
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return cmd;
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}
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static void __init spectre_v2_select_mitigation(void)
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{
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enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
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enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
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/*
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* If the CPU is not affected and the command line mode is NONE or AUTO
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* then nothing to do.
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*/
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if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
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(cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
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return;
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switch (cmd) {
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case SPECTRE_V2_CMD_NONE:
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return;
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case SPECTRE_V2_CMD_FORCE:
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case SPECTRE_V2_CMD_AUTO:
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if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
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mode = SPECTRE_V2_IBRS_ENHANCED;
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/* Force it so VMEXIT will restore correctly */
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x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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goto specv2_set_mode;
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}
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if (IS_ENABLED(CONFIG_RETPOLINE))
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goto retpoline_auto;
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break;
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case SPECTRE_V2_CMD_RETPOLINE_AMD:
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if (IS_ENABLED(CONFIG_RETPOLINE))
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goto retpoline_amd;
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break;
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case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
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if (IS_ENABLED(CONFIG_RETPOLINE))
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goto retpoline_generic;
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break;
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case SPECTRE_V2_CMD_RETPOLINE:
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if (IS_ENABLED(CONFIG_RETPOLINE))
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goto retpoline_auto;
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break;
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}
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pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
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return;
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retpoline_auto:
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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retpoline_amd:
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if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
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pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
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goto retpoline_generic;
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}
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mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
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SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
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setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
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setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
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} else {
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retpoline_generic:
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mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
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SPECTRE_V2_RETPOLINE_MINIMAL;
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setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
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}
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specv2_set_mode:
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spectre_v2_enabled = mode;
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pr_info("%s\n", spectre_v2_strings[mode]);
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/*
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* If spectre v2 protection has been enabled, unconditionally fill
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* RSB during a context switch; this protects against two independent
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* issues:
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*
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* - RSB underflow (and switch to BTB) on Skylake+
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* - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
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*/
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setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
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pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
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/* Initialize Indirect Branch Prediction Barrier if supported */
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if (boot_cpu_has(X86_FEATURE_IBPB)) {
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setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
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pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
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}
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/*
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* Retpoline means the kernel is safe because it has no indirect
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* branches. Enhanced IBRS protects firmware too, so, enable restricted
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* speculation around firmware calls only when Enhanced IBRS isn't
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* supported.
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*
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* Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
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* the user might select retpoline on the kernel command line and if
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* the CPU supports Enhanced IBRS, kernel might un-intentionally not
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* enable IBRS around firmware calls.
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*/
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if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
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setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
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pr_info("Enabling Restricted Speculation for firmware calls\n");
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}
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}
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#undef pr_fmt
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#define pr_fmt(fmt) "Speculative Store Bypass: " fmt
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static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
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/* The kernel command line selection */
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enum ssb_mitigation_cmd {
|
|
SPEC_STORE_BYPASS_CMD_NONE,
|
|
SPEC_STORE_BYPASS_CMD_AUTO,
|
|
SPEC_STORE_BYPASS_CMD_ON,
|
|
SPEC_STORE_BYPASS_CMD_PRCTL,
|
|
SPEC_STORE_BYPASS_CMD_SECCOMP,
|
|
};
|
|
|
|
static const char *ssb_strings[] = {
|
|
[SPEC_STORE_BYPASS_NONE] = "Vulnerable",
|
|
[SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
|
|
[SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
|
|
[SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
|
|
};
|
|
|
|
static const struct {
|
|
const char *option;
|
|
enum ssb_mitigation_cmd cmd;
|
|
} ssb_mitigation_options[] = {
|
|
{ "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
|
|
{ "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
|
|
{ "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
|
|
{ "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
|
|
{ "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
|
|
};
|
|
|
|
static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
|
|
{
|
|
enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
|
|
char arg[20];
|
|
int ret, i;
|
|
|
|
if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
|
|
return SPEC_STORE_BYPASS_CMD_NONE;
|
|
} else {
|
|
ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
|
|
arg, sizeof(arg));
|
|
if (ret < 0)
|
|
return SPEC_STORE_BYPASS_CMD_AUTO;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
|
|
if (!match_option(arg, ret, ssb_mitigation_options[i].option))
|
|
continue;
|
|
|
|
cmd = ssb_mitigation_options[i].cmd;
|
|
break;
|
|
}
|
|
|
|
if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
|
|
pr_err("unknown option (%s). Switching to AUTO select\n", arg);
|
|
return SPEC_STORE_BYPASS_CMD_AUTO;
|
|
}
|
|
}
|
|
|
|
return cmd;
|
|
}
|
|
|
|
static enum ssb_mitigation __init __ssb_select_mitigation(void)
|
|
{
|
|
enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
|
|
enum ssb_mitigation_cmd cmd;
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_SSBD))
|
|
return mode;
|
|
|
|
cmd = ssb_parse_cmdline();
|
|
if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
|
|
(cmd == SPEC_STORE_BYPASS_CMD_NONE ||
|
|
cmd == SPEC_STORE_BYPASS_CMD_AUTO))
|
|
return mode;
|
|
|
|
switch (cmd) {
|
|
case SPEC_STORE_BYPASS_CMD_AUTO:
|
|
case SPEC_STORE_BYPASS_CMD_SECCOMP:
|
|
/*
|
|
* Choose prctl+seccomp as the default mode if seccomp is
|
|
* enabled.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_SECCOMP))
|
|
mode = SPEC_STORE_BYPASS_SECCOMP;
|
|
else
|
|
mode = SPEC_STORE_BYPASS_PRCTL;
|
|
break;
|
|
case SPEC_STORE_BYPASS_CMD_ON:
|
|
mode = SPEC_STORE_BYPASS_DISABLE;
|
|
break;
|
|
case SPEC_STORE_BYPASS_CMD_PRCTL:
|
|
mode = SPEC_STORE_BYPASS_PRCTL;
|
|
break;
|
|
case SPEC_STORE_BYPASS_CMD_NONE:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* We have three CPU feature flags that are in play here:
|
|
* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
|
|
* - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
|
|
* - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
|
|
*/
|
|
if (mode == SPEC_STORE_BYPASS_DISABLE) {
|
|
setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
|
|
/*
|
|
* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
|
|
* use a completely different MSR and bit dependent on family.
|
|
*/
|
|
if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
|
|
!static_cpu_has(X86_FEATURE_AMD_SSBD)) {
|
|
x86_amd_ssb_disable();
|
|
} else {
|
|
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
|
|
x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
|
|
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
|
|
}
|
|
}
|
|
|
|
return mode;
|
|
}
|
|
|
|
static void ssb_select_mitigation(void)
|
|
{
|
|
ssb_mode = __ssb_select_mitigation();
|
|
|
|
if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
|
|
pr_info("%s\n", ssb_strings[ssb_mode]);
|
|
}
|
|
|
|
#undef pr_fmt
|
|
#define pr_fmt(fmt) "Speculation prctl: " fmt
|
|
|
|
static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
|
|
{
|
|
bool update;
|
|
|
|
if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
|
|
ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
|
|
return -ENXIO;
|
|
|
|
switch (ctrl) {
|
|
case PR_SPEC_ENABLE:
|
|
/* If speculation is force disabled, enable is not allowed */
|
|
if (task_spec_ssb_force_disable(task))
|
|
return -EPERM;
|
|
task_clear_spec_ssb_disable(task);
|
|
update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
|
|
break;
|
|
case PR_SPEC_DISABLE:
|
|
task_set_spec_ssb_disable(task);
|
|
update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
|
|
break;
|
|
case PR_SPEC_FORCE_DISABLE:
|
|
task_set_spec_ssb_disable(task);
|
|
task_set_spec_ssb_force_disable(task);
|
|
update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
|
|
break;
|
|
default:
|
|
return -ERANGE;
|
|
}
|
|
|
|
/*
|
|
* If being set on non-current task, delay setting the CPU
|
|
* mitigation until it is next scheduled.
|
|
*/
|
|
if (task == current && update)
|
|
speculative_store_bypass_update_current();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
|
|
unsigned long ctrl)
|
|
{
|
|
switch (which) {
|
|
case PR_SPEC_STORE_BYPASS:
|
|
return ssb_prctl_set(task, ctrl);
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SECCOMP
|
|
void arch_seccomp_spec_mitigate(struct task_struct *task)
|
|
{
|
|
if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
|
|
ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
|
|
}
|
|
#endif
|
|
|
|
static int ssb_prctl_get(struct task_struct *task)
|
|
{
|
|
switch (ssb_mode) {
|
|
case SPEC_STORE_BYPASS_DISABLE:
|
|
return PR_SPEC_DISABLE;
|
|
case SPEC_STORE_BYPASS_SECCOMP:
|
|
case SPEC_STORE_BYPASS_PRCTL:
|
|
if (task_spec_ssb_force_disable(task))
|
|
return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
|
|
if (task_spec_ssb_disable(task))
|
|
return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
|
|
return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
|
|
default:
|
|
if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
|
|
return PR_SPEC_ENABLE;
|
|
return PR_SPEC_NOT_AFFECTED;
|
|
}
|
|
}
|
|
|
|
int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
|
|
{
|
|
switch (which) {
|
|
case PR_SPEC_STORE_BYPASS:
|
|
return ssb_prctl_get(task);
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
void x86_spec_ctrl_setup_ap(void)
|
|
{
|
|
if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
|
|
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
|
|
|
|
if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
|
|
x86_amd_ssb_disable();
|
|
}
|
|
|
|
#undef pr_fmt
|
|
#define pr_fmt(fmt) "L1TF: " fmt
|
|
|
|
/* Default mitigation for L1TF-affected CPUs */
|
|
enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
|
|
#if IS_ENABLED(CONFIG_KVM_INTEL)
|
|
EXPORT_SYMBOL_GPL(l1tf_mitigation);
|
|
#endif
|
|
enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
|
|
EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
|
|
|
|
/*
|
|
* These CPUs all support 44bits physical address space internally in the
|
|
* cache but CPUID can report a smaller number of physical address bits.
|
|
*
|
|
* The L1TF mitigation uses the top most address bit for the inversion of
|
|
* non present PTEs. When the installed memory reaches into the top most
|
|
* address bit due to memory holes, which has been observed on machines
|
|
* which report 36bits physical address bits and have 32G RAM installed,
|
|
* then the mitigation range check in l1tf_select_mitigation() triggers.
|
|
* This is a false positive because the mitigation is still possible due to
|
|
* the fact that the cache uses 44bit internally. Use the cache bits
|
|
* instead of the reported physical bits and adjust them on the affected
|
|
* machines to 44bit if the reported bits are less than 44.
|
|
*/
|
|
static void override_cache_bits(struct cpuinfo_x86 *c)
|
|
{
|
|
if (c->x86 != 6)
|
|
return;
|
|
|
|
switch (c->x86_model) {
|
|
case INTEL_FAM6_NEHALEM:
|
|
case INTEL_FAM6_WESTMERE:
|
|
case INTEL_FAM6_SANDYBRIDGE:
|
|
case INTEL_FAM6_IVYBRIDGE:
|
|
case INTEL_FAM6_HASWELL_CORE:
|
|
case INTEL_FAM6_HASWELL_ULT:
|
|
case INTEL_FAM6_HASWELL_GT3E:
|
|
case INTEL_FAM6_BROADWELL_CORE:
|
|
case INTEL_FAM6_BROADWELL_GT3E:
|
|
case INTEL_FAM6_SKYLAKE_MOBILE:
|
|
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
|
case INTEL_FAM6_KABYLAKE_MOBILE:
|
|
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
|
if (c->x86_cache_bits < 44)
|
|
c->x86_cache_bits = 44;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void __init l1tf_select_mitigation(void)
|
|
{
|
|
u64 half_pa;
|
|
|
|
if (!boot_cpu_has_bug(X86_BUG_L1TF))
|
|
return;
|
|
|
|
override_cache_bits(&boot_cpu_data);
|
|
|
|
switch (l1tf_mitigation) {
|
|
case L1TF_MITIGATION_OFF:
|
|
case L1TF_MITIGATION_FLUSH_NOWARN:
|
|
case L1TF_MITIGATION_FLUSH:
|
|
break;
|
|
case L1TF_MITIGATION_FLUSH_NOSMT:
|
|
case L1TF_MITIGATION_FULL:
|
|
cpu_smt_disable(false);
|
|
break;
|
|
case L1TF_MITIGATION_FULL_FORCE:
|
|
cpu_smt_disable(true);
|
|
break;
|
|
}
|
|
|
|
#if CONFIG_PGTABLE_LEVELS == 2
|
|
pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
|
|
return;
|
|
#endif
|
|
|
|
half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
|
|
if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
|
|
pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
|
|
pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
|
|
half_pa);
|
|
pr_info("However, doing so will make a part of your RAM unusable.\n");
|
|
pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
|
|
return;
|
|
}
|
|
|
|
setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
|
|
}
|
|
|
|
static int __init l1tf_cmdline(char *str)
|
|
{
|
|
if (!boot_cpu_has_bug(X86_BUG_L1TF))
|
|
return 0;
|
|
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "off"))
|
|
l1tf_mitigation = L1TF_MITIGATION_OFF;
|
|
else if (!strcmp(str, "flush,nowarn"))
|
|
l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
|
|
else if (!strcmp(str, "flush"))
|
|
l1tf_mitigation = L1TF_MITIGATION_FLUSH;
|
|
else if (!strcmp(str, "flush,nosmt"))
|
|
l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
|
|
else if (!strcmp(str, "full"))
|
|
l1tf_mitigation = L1TF_MITIGATION_FULL;
|
|
else if (!strcmp(str, "full,force"))
|
|
l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
|
|
|
|
return 0;
|
|
}
|
|
early_param("l1tf", l1tf_cmdline);
|
|
|
|
#undef pr_fmt
|
|
|
|
#ifdef CONFIG_SYSFS
|
|
|
|
#define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
|
|
|
|
#if IS_ENABLED(CONFIG_KVM_INTEL)
|
|
static const char *l1tf_vmx_states[] = {
|
|
[VMENTER_L1D_FLUSH_AUTO] = "auto",
|
|
[VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
|
|
[VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
|
|
[VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
|
|
[VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
|
|
[VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
|
|
};
|
|
|
|
static ssize_t l1tf_show_state(char *buf)
|
|
{
|
|
if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
|
|
return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
|
|
|
|
if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
|
|
(l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
|
|
cpu_smt_control == CPU_SMT_ENABLED))
|
|
return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
|
|
l1tf_vmx_states[l1tf_vmx_mitigation]);
|
|
|
|
return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
|
|
l1tf_vmx_states[l1tf_vmx_mitigation],
|
|
cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
|
|
}
|
|
#else
|
|
static ssize_t l1tf_show_state(char *buf)
|
|
{
|
|
return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
|
|
}
|
|
#endif
|
|
|
|
static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
|
|
char *buf, unsigned int bug)
|
|
{
|
|
if (!boot_cpu_has_bug(bug))
|
|
return sprintf(buf, "Not affected\n");
|
|
|
|
switch (bug) {
|
|
case X86_BUG_CPU_MELTDOWN:
|
|
if (boot_cpu_has(X86_FEATURE_PTI))
|
|
return sprintf(buf, "Mitigation: PTI\n");
|
|
|
|
if (hypervisor_is_type(X86_HYPER_XEN_PV))
|
|
return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
|
|
|
|
break;
|
|
|
|
case X86_BUG_SPECTRE_V1:
|
|
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
|
|
|
|
case X86_BUG_SPECTRE_V2:
|
|
return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
|
|
boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
|
|
boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
|
|
spectre_v2_module_string());
|
|
|
|
case X86_BUG_SPEC_STORE_BYPASS:
|
|
return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
|
|
|
|
case X86_BUG_L1TF:
|
|
if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
|
|
return l1tf_show_state(buf);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return sprintf(buf, "Vulnerable\n");
|
|
}
|
|
|
|
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
|
|
}
|
|
|
|
ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
|
|
}
|
|
|
|
ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
|
|
}
|
|
|
|
ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
|
|
}
|
|
|
|
ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
|
|
}
|
|
#endif
|