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44ac5958a6
Check that PML is actually enabled before setting the mask to force a
SPTE to be write-protected. The bits used for the !AD_ENABLED case are
in the upper half of the SPTE. With 64-bit paging and EPT, these bits
are ignored, but with 32-bit PAE paging they are reserved. Setting them
for L2 SPTEs without checking PML breaks NPT on 32-bit KVM.
Fixes: 1f4e5fc83a ("KVM: x86: fix nested guest live migration with PML")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210225204749.1512652-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
160 lines
4.7 KiB
C
160 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_MMU_INTERNAL_H
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#define __KVM_X86_MMU_INTERNAL_H
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_host.h>
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#undef MMU_DEBUG
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#ifdef MMU_DEBUG
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extern bool dbg;
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#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
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#define rmap_printk(fmt, args...) do { if (dbg) printk("%s: " fmt, __func__, ## args); } while (0)
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#define MMU_WARN_ON(x) WARN_ON(x)
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#else
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#define pgprintk(x...) do { } while (0)
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#define rmap_printk(x...) do { } while (0)
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#define MMU_WARN_ON(x) do { } while (0)
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#endif
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struct kvm_mmu_page {
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struct list_head link;
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struct hlist_node hash_link;
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struct list_head lpage_disallowed_link;
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bool unsync;
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u8 mmu_valid_gen;
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bool mmio_cached;
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bool lpage_disallowed; /* Can't be replaced by an equiv large page */
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/*
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* The following two entries are used to key the shadow page in the
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* hash table.
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*/
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union kvm_mmu_page_role role;
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gfn_t gfn;
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u64 *spt;
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/* hold the gfn of each spte inside spt */
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gfn_t *gfns;
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int root_count; /* Currently serving as active root */
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unsigned int unsync_children;
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struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */
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DECLARE_BITMAP(unsync_child_bitmap, 512);
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#ifdef CONFIG_X86_32
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/*
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* Used out of the mmu-lock to avoid reading spte values while an
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* update is in progress; see the comments in __get_spte_lockless().
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*/
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int clear_spte_count;
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#endif
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/* Number of writes since the last time traversal visited this page. */
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atomic_t write_flooding_count;
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#ifdef CONFIG_X86_64
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bool tdp_mmu_page;
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/* Used for freeing the page asyncronously if it is a TDP MMU page. */
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struct rcu_head rcu_head;
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#endif
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};
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extern struct kmem_cache *mmu_page_header_cache;
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static inline struct kvm_mmu_page *to_shadow_page(hpa_t shadow_page)
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{
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struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
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return (struct kvm_mmu_page *)page_private(page);
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}
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static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep)
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{
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return to_shadow_page(__pa(sptep));
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}
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static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
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{
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/*
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* When using the EPT page-modification log, the GPAs in the CPU dirty
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* log would come from L2 rather than L1. Therefore, we need to rely
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* on write protection to record dirty pages, which bypasses PML, since
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* writes now result in a vmexit. Note, the check on CPU dirty logging
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* being enabled is mandatory as the bits used to denote WP-only SPTEs
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* are reserved for NPT w/ PAE (32-bit KVM).
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*/
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return vcpu->arch.mmu == &vcpu->arch.guest_mmu &&
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kvm_x86_ops.cpu_dirty_log_size;
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}
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bool is_nx_huge_page_enabled(void);
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bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
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bool can_unsync);
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void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
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struct kvm_memory_slot *slot, u64 gfn);
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void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
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u64 start_gfn, u64 pages);
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static inline void kvm_mmu_get_root(struct kvm *kvm, struct kvm_mmu_page *sp)
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{
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BUG_ON(!sp->root_count);
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lockdep_assert_held(&kvm->mmu_lock);
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++sp->root_count;
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}
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static inline bool kvm_mmu_put_root(struct kvm *kvm, struct kvm_mmu_page *sp)
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{
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lockdep_assert_held(&kvm->mmu_lock);
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--sp->root_count;
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return !sp->root_count;
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}
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/*
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* Return values of handle_mmio_page_fault, mmu.page_fault, and fast_page_fault().
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*
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* RET_PF_RETRY: let CPU fault again on the address.
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* RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
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* RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
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* RET_PF_FIXED: The faulting entry has been fixed.
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* RET_PF_SPURIOUS: The faulting entry was already fixed, e.g. by another vCPU.
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*/
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enum {
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RET_PF_RETRY = 0,
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RET_PF_EMULATE,
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RET_PF_INVALID,
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RET_PF_FIXED,
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RET_PF_SPURIOUS,
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};
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/* Bits which may be returned by set_spte() */
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#define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
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#define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
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#define SET_SPTE_SPURIOUS BIT(2)
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int kvm_mmu_max_mapping_level(struct kvm *kvm, struct kvm_memory_slot *slot,
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gfn_t gfn, kvm_pfn_t pfn, int max_level);
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int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
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int max_level, kvm_pfn_t *pfnp,
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bool huge_page_disallowed, int *req_level);
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void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
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kvm_pfn_t *pfnp, int *goal_levelp);
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bool is_nx_huge_page_enabled(void);
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void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc);
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void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp);
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void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp);
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#endif /* __KVM_X86_MMU_INTERNAL_H */
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