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c3ad321932
- Use clk_hw pointers in socfpga driver - Cleanup parent data in qcom clk drivers * clk-cleanup: clk: Drop double "if" in clk_core_determine_round_nolock() comment clk: at91: Trivial typo fixes in the file sama7g5.c clk: use clk_core_enable_lock() a bit more * clk-renesas: clk: renesas: Zero init clk_init_data clk: renesas: Couple of spelling fixes clk: renesas: r8a779a0: Add CMT clocks clk: renesas: r8a7795: Add TMU clocks clk: renesas: r8a779a0: Add TSC clock clk: renesas: r8a779a0: Add TMU clocks clk: renesas: r8a77965: Add DAB clock clk: renesas: r8a77990: Add DAB clock * clk-socfpga: clk: socfpga: remove redundant initialization of variable div clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return clk: socfpga: Fix code formatting clk: socfpga: Convert to s10/agilex/n5x to use clk_hw clk: socfpga: arria10: convert to use clk_hw clk: socfpga: use clk_hw_register for a5/c5 * clk-allwinner: clk: sunxi: Demote non-conformant kernel-doc headers clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll * clk-qcom: (45 commits) clk: qcom: rpmh: add support for SDX55 rpmh IPA clock clk: qcom: gcc-sdm845: get rid of the test clock clk: qcom: convert SDM845 Global Clock Controller to parent_data dt-bindings: clock: separate SDM845 GCC clock bindings clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents clk: qcom: videocc-sm8250: use parent_hws where possible clk: qcom: videocc-sm8150: use parent_hws where possible clk: qcom: gpucc-sm8250: use parent_hws where possible clk: qcom: gpucc-sm8150: use parent_hws where possible clk: qcom: gcc-sm8350: use parent_hws where possible clk: qcom: gcc-sm8250: use parent_hws where possible clk: qcom: gcc-sm8150: use parent_hws where possible clk: qcom: gcc-sdx55: use parent_hws where possible ...
253 lines
6.1 KiB
C
253 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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*
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* Based from clk-highbank.c
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include "clk.h"
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#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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#define SOCFPGA_MMC_CLK "sdmmc_clk"
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#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
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/* SDMMC Group for System Manager defines */
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#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
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static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
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{
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u32 l4_src;
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u32 perpll_src;
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const char *name = clk_hw_get_name(hwclk);
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if (streq(name, SOCFPGA_L4_MP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return l4_src &= 0x1;
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}
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if (streq(name, SOCFPGA_L4_SP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return !!(l4_src & 2);
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}
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perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(name, SOCFPGA_MMC_CLK))
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return perpll_src &= 0x3;
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if (streq(name, SOCFPGA_NAND_CLK) ||
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streq(name, SOCFPGA_NAND_X_CLK))
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return (perpll_src >> 2) & 3;
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/* QSPI clock */
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return (perpll_src >> 4) & 3;
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}
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static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
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{
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u32 src_reg;
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const char *name = clk_hw_get_name(hwclk);
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if (streq(name, SOCFPGA_L4_MP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x1;
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src_reg |= parent;
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x2;
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src_reg |= (parent << 1);
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(name, SOCFPGA_MMC_CLK)) {
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src_reg &= ~0x3;
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src_reg |= parent;
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} else if (streq(name, SOCFPGA_NAND_CLK) ||
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streq(name, SOCFPGA_NAND_X_CLK)) {
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src_reg &= ~0xC;
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src_reg |= (parent << 2);
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} else {/* QSPI clock */
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src_reg &= ~0x30;
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src_reg |= (parent << 4);
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}
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writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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}
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return 0;
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}
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static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div)
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div = socfpgaclk->fixed_div;
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else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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/* Check for GPIO_DB_CLK by its offset */
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if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
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div = val + 1;
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else
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static int socfpga_clk_prepare(struct clk_hw *hwclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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struct regmap *sys_mgr_base_addr;
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int i;
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u32 hs_timing;
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u32 clk_phase[2];
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if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
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sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
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if (IS_ERR(sys_mgr_base_addr)) {
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pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
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return -EINVAL;
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}
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for (i = 0; i < 2; i++) {
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switch (socfpgaclk->clk_phase[i]) {
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case 0:
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clk_phase[i] = 0;
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break;
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case 45:
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clk_phase[i] = 1;
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break;
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case 90:
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clk_phase[i] = 2;
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break;
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case 135:
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clk_phase[i] = 3;
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break;
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case 180:
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clk_phase[i] = 4;
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break;
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case 225:
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clk_phase[i] = 5;
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break;
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case 270:
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clk_phase[i] = 6;
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break;
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case 315:
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clk_phase[i] = 7;
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break;
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default:
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clk_phase[i] = 0;
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break;
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}
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}
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hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
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regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
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hs_timing);
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}
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return 0;
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}
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static struct clk_ops gateclk_ops = {
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.prepare = socfpga_clk_prepare,
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.recalc_rate = socfpga_clk_recalc_rate,
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.get_parent = socfpga_clk_get_parent,
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.set_parent = socfpga_clk_set_parent,
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};
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void __init socfpga_gate_init(struct device_node *node)
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{
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u32 clk_gate[2];
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u32 div_reg[3];
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u32 clk_phase[2];
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u32 fixed_div;
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_ops *ops;
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int rc;
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int err;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (WARN_ON(!socfpga_clk))
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return;
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ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
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if (WARN_ON(!ops))
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return;
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rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
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if (rc)
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clk_gate[0] = 0;
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if (clk_gate[0]) {
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socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
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socfpga_clk->hw.bit_idx = clk_gate[1];
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ops->enable = clk_gate_ops.enable;
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ops->disable = clk_gate_ops.disable;
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}
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (rc)
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socfpga_clk->fixed_div = 0;
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else
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socfpga_clk->fixed_div = fixed_div;
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rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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if (!rc) {
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socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
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socfpga_clk->shift = div_reg[1];
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socfpga_clk->width = div_reg[2];
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} else {
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socfpga_clk->div_reg = NULL;
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}
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rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
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if (!rc) {
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socfpga_clk->clk_phase[0] = clk_phase[0];
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socfpga_clk->clk_phase[1] = clk_phase[1];
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}
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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if (init.num_parents < 2) {
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ops->get_parent = NULL;
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ops->set_parent = NULL;
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}
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init.parent_names = parent_name;
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socfpga_clk->hw.hw.init = &init;
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hw_clk = &socfpga_clk->hw.hw;
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err = clk_hw_register(NULL, hw_clk);
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if (err) {
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kfree(socfpga_clk);
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return;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
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if (WARN_ON(rc))
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return;
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}
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