linux/drivers/clk/ux500/reset-prcc.h
Linus Walleij b14cbdfd46 clk: ux500: Add driver for the reset portions of PRCC
The Ux500 PRCC (peripheral reset and clock controller) can also
control reset of the IP blocks, not just clocks. As the PRCC is probed
as a clock controller and we have other platforms implementing combined
clock and reset controllers, follow this pattern and implement the PRCC
rest controller as part of the clock driver.

The reset controller needs to be selected from the machine as Ux500 has
traditionally selected its mandatory subsystem prerequisites from there.

Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
[sboyd@kernel.org: Dropped allocation error message]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26 18:06:05 -07:00

24 lines
566 B
C

/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __RESET_PRCC_H
#define __RESET_PRCC_H
#include <linux/reset-controller.h>
#include <linux/io.h>
/**
* struct u8500_prcc_reset - U8500 PRCC reset controller state
* @rcdev: reset controller device
* @phy_base: the physical base address for each PRCC block
* @base: the remapped PRCC bases
*/
struct u8500_prcc_reset {
struct reset_controller_dev rcdev;
u32 phy_base[CLKRST_MAX];
void __iomem *base[CLKRST_MAX];
};
void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur);
#endif