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5c70854130
This makes use of the struct_size() macro to calculate the size of the struct axi_spi_engine when allocating it. Suggested-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://msgid.link/r/20240304-mainline-axi-spi-engine-small-cleanups-v2-3-5b14ed729a31@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
686 lines
18 KiB
C
686 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPI-Engine SPI controller driver
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* Copyright 2015 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/fpga/adi-axi-common.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/overflow.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define SPI_ENGINE_REG_RESET 0x40
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#define SPI_ENGINE_REG_INT_ENABLE 0x80
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#define SPI_ENGINE_REG_INT_PENDING 0x84
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#define SPI_ENGINE_REG_INT_SOURCE 0x88
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#define SPI_ENGINE_REG_SYNC_ID 0xc0
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#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
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#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
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#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
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#define SPI_ENGINE_REG_CMD_FIFO 0xe0
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#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
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#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
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#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
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#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
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#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
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#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
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#define SPI_ENGINE_INT_SYNC BIT(3)
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#define SPI_ENGINE_CONFIG_CPHA BIT(0)
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#define SPI_ENGINE_CONFIG_CPOL BIT(1)
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#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
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#define SPI_ENGINE_INST_TRANSFER 0x0
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#define SPI_ENGINE_INST_ASSERT 0x1
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#define SPI_ENGINE_INST_WRITE 0x2
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#define SPI_ENGINE_INST_MISC 0x3
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#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
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#define SPI_ENGINE_CMD_REG_CONFIG 0x1
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#define SPI_ENGINE_CMD_REG_XFER_BITS 0x2
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#define SPI_ENGINE_MISC_SYNC 0x0
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#define SPI_ENGINE_MISC_SLEEP 0x1
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#define SPI_ENGINE_TRANSFER_WRITE 0x1
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#define SPI_ENGINE_TRANSFER_READ 0x2
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/* Arbitrary sync ID for use by host->cur_msg */
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#define AXI_SPI_ENGINE_CUR_MSG_SYNC_ID 0x1
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#define SPI_ENGINE_CMD(inst, arg1, arg2) \
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(((inst) << 12) | ((arg1) << 8) | (arg2))
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#define SPI_ENGINE_CMD_TRANSFER(flags, n) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
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#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
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#define SPI_ENGINE_CMD_WRITE(reg, val) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
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#define SPI_ENGINE_CMD_SLEEP(delay) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
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#define SPI_ENGINE_CMD_SYNC(id) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
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struct spi_engine_program {
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unsigned int length;
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uint16_t instructions[] __counted_by(length);
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};
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/**
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* struct spi_engine_message_state - SPI engine per-message state
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*/
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struct spi_engine_message_state {
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/** @cmd_length: Number of elements in cmd_buf array. */
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unsigned cmd_length;
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/** @cmd_buf: Array of commands not yet written to CMD FIFO. */
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const uint16_t *cmd_buf;
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/** @tx_xfer: Next xfer with tx_buf not yet fully written to TX FIFO. */
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struct spi_transfer *tx_xfer;
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/** @tx_length: Size of tx_buf in bytes. */
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unsigned int tx_length;
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/** @tx_buf: Bytes not yet written to TX FIFO. */
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const uint8_t *tx_buf;
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/** @rx_xfer: Next xfer with rx_buf not yet fully written to RX FIFO. */
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struct spi_transfer *rx_xfer;
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/** @rx_length: Size of tx_buf in bytes. */
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unsigned int rx_length;
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/** @rx_buf: Bytes not yet written to the RX FIFO. */
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uint8_t *rx_buf;
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};
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struct spi_engine {
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struct clk *clk;
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struct clk *ref_clk;
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spinlock_t lock;
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void __iomem *base;
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struct spi_engine_message_state msg_state;
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struct completion msg_complete;
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unsigned int int_enable;
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};
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static void spi_engine_program_add_cmd(struct spi_engine_program *p,
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bool dry, uint16_t cmd)
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{
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p->length++;
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if (!dry)
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p->instructions[p->length - 1] = cmd;
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}
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static unsigned int spi_engine_get_config(struct spi_device *spi)
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{
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unsigned int config = 0;
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if (spi->mode & SPI_CPOL)
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config |= SPI_ENGINE_CONFIG_CPOL;
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if (spi->mode & SPI_CPHA)
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config |= SPI_ENGINE_CONFIG_CPHA;
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if (spi->mode & SPI_3WIRE)
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config |= SPI_ENGINE_CONFIG_3WIRE;
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return config;
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}
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static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
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struct spi_transfer *xfer)
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{
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unsigned int len;
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if (xfer->bits_per_word <= 8)
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len = xfer->len;
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else if (xfer->bits_per_word <= 16)
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len = xfer->len / 2;
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else
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len = xfer->len / 4;
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while (len) {
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unsigned int n = min(len, 256U);
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unsigned int flags = 0;
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if (xfer->tx_buf)
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flags |= SPI_ENGINE_TRANSFER_WRITE;
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if (xfer->rx_buf)
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flags |= SPI_ENGINE_TRANSFER_READ;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
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len -= n;
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}
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}
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static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
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int delay_ns, u32 sclk_hz)
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{
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unsigned int t;
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/* negative delay indicates error, e.g. from spi_delay_to_ns() */
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if (delay_ns <= 0)
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return;
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/* rounding down since executing the instruction adds a couple of ticks delay */
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t = DIV_ROUND_DOWN_ULL((u64)delay_ns * sclk_hz, NSEC_PER_SEC);
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while (t) {
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unsigned int n = min(t, 256U);
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spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
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t -= n;
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}
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}
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static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
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struct spi_device *spi, bool assert)
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{
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unsigned int mask = 0xff;
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if (assert)
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mask ^= BIT(spi_get_chipselect(spi, 0));
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spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(0, mask));
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}
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/*
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* Performs precompile steps on the message.
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*
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* The SPI core does most of the message/transfer validation and filling in
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* fields for us via __spi_validate(). This fixes up anything remaining not
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* done there.
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*
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* NB: This is separate from spi_engine_compile_message() because the latter
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* is called twice and would otherwise result in double-evaluation.
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*/
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static void spi_engine_precompile_message(struct spi_message *msg)
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{
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unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz;
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struct spi_transfer *xfer;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz);
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xfer->effective_speed_hz = max_hz / min(clk_div, 256U);
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}
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}
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static void spi_engine_compile_message(struct spi_message *msg, bool dry,
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struct spi_engine_program *p)
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{
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struct spi_device *spi = msg->spi;
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struct spi_controller *host = spi->controller;
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struct spi_transfer *xfer;
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int clk_div, new_clk_div;
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bool keep_cs = false;
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u8 bits_per_word = 0;
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clk_div = 1;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
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spi_engine_get_config(spi)));
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xfer = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list);
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spi_engine_gen_cs(p, dry, spi, !xfer->cs_off);
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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new_clk_div = host->max_speed_hz / xfer->effective_speed_hz;
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if (new_clk_div != clk_div) {
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clk_div = new_clk_div;
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/* actual divider used is register value + 1 */
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
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clk_div - 1));
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}
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if (bits_per_word != xfer->bits_per_word) {
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bits_per_word = xfer->bits_per_word;
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_XFER_BITS,
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bits_per_word));
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}
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spi_engine_gen_xfer(p, dry, xfer);
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spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer),
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xfer->effective_speed_hz);
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if (xfer->cs_change) {
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if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
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keep_cs = true;
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} else {
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if (!xfer->cs_off)
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spi_engine_gen_cs(p, dry, spi, false);
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spi_engine_gen_sleep(p, dry, spi_delay_to_ns(
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&xfer->cs_change_delay, xfer),
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xfer->effective_speed_hz);
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if (!list_next_entry(xfer, transfer_list)->cs_off)
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spi_engine_gen_cs(p, dry, spi, true);
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}
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} else if (!list_is_last(&xfer->transfer_list, &msg->transfers) &&
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xfer->cs_off != list_next_entry(xfer, transfer_list)->cs_off) {
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spi_engine_gen_cs(p, dry, spi, xfer->cs_off);
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}
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}
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if (!keep_cs)
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spi_engine_gen_cs(p, dry, spi, false);
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/*
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* Restore clockdiv to default so that future gen_sleep commands don't
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* have to be aware of the current register state.
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*/
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if (clk_div != 1)
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0));
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}
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static void spi_engine_xfer_next(struct spi_message *msg,
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struct spi_transfer **_xfer)
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{
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struct spi_transfer *xfer = *_xfer;
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if (!xfer) {
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xfer = list_first_entry(&msg->transfers,
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struct spi_transfer, transfer_list);
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} else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
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xfer = NULL;
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} else {
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xfer = list_next_entry(xfer, transfer_list);
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}
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*_xfer = xfer;
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}
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static void spi_engine_tx_next(struct spi_message *msg)
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{
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struct spi_engine_message_state *st = msg->state;
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struct spi_transfer *xfer = st->tx_xfer;
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do {
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spi_engine_xfer_next(msg, &xfer);
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} while (xfer && !xfer->tx_buf);
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st->tx_xfer = xfer;
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if (xfer) {
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st->tx_length = xfer->len;
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st->tx_buf = xfer->tx_buf;
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} else {
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st->tx_buf = NULL;
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}
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}
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static void spi_engine_rx_next(struct spi_message *msg)
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{
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struct spi_engine_message_state *st = msg->state;
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struct spi_transfer *xfer = st->rx_xfer;
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do {
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spi_engine_xfer_next(msg, &xfer);
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} while (xfer && !xfer->rx_buf);
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st->rx_xfer = xfer;
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if (xfer) {
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st->rx_length = xfer->len;
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st->rx_buf = xfer->rx_buf;
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} else {
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st->rx_buf = NULL;
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}
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}
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static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine,
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struct spi_message *msg)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
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struct spi_engine_message_state *st = msg->state;
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unsigned int n, m, i;
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const uint16_t *buf;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
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while (n && st->cmd_length) {
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m = min(n, st->cmd_length);
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buf = st->cmd_buf;
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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st->cmd_buf += m;
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st->cmd_length -= m;
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n -= m;
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}
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return st->cmd_length != 0;
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}
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static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine,
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struct spi_message *msg)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
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struct spi_engine_message_state *st = msg->state;
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unsigned int n, m, i;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
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while (n && st->tx_length) {
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if (st->tx_xfer->bits_per_word <= 8) {
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const u8 *buf = st->tx_buf;
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m = min(n, st->tx_length);
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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st->tx_buf += m;
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st->tx_length -= m;
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} else if (st->tx_xfer->bits_per_word <= 16) {
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const u16 *buf = (const u16 *)st->tx_buf;
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m = min(n, st->tx_length / 2);
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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st->tx_buf += m * 2;
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st->tx_length -= m * 2;
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} else {
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const u32 *buf = (const u32 *)st->tx_buf;
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m = min(n, st->tx_length / 4);
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for (i = 0; i < m; i++)
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writel_relaxed(buf[i], addr);
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st->tx_buf += m * 4;
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st->tx_length -= m * 4;
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}
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n -= m;
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if (st->tx_length == 0)
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spi_engine_tx_next(msg);
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}
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return st->tx_length != 0;
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}
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static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine,
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struct spi_message *msg)
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{
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void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
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struct spi_engine_message_state *st = msg->state;
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unsigned int n, m, i;
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n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
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while (n && st->rx_length) {
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if (st->rx_xfer->bits_per_word <= 8) {
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u8 *buf = st->rx_buf;
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m = min(n, st->rx_length);
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for (i = 0; i < m; i++)
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buf[i] = readl_relaxed(addr);
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st->rx_buf += m;
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st->rx_length -= m;
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} else if (st->rx_xfer->bits_per_word <= 16) {
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u16 *buf = (u16 *)st->rx_buf;
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m = min(n, st->rx_length / 2);
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for (i = 0; i < m; i++)
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buf[i] = readl_relaxed(addr);
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st->rx_buf += m * 2;
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st->rx_length -= m * 2;
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} else {
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u32 *buf = (u32 *)st->rx_buf;
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m = min(n, st->rx_length / 4);
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for (i = 0; i < m; i++)
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buf[i] = readl_relaxed(addr);
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st->rx_buf += m * 4;
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st->rx_length -= m * 4;
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}
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n -= m;
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if (st->rx_length == 0)
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spi_engine_rx_next(msg);
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}
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return st->rx_length != 0;
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}
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static irqreturn_t spi_engine_irq(int irq, void *devid)
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{
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struct spi_controller *host = devid;
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struct spi_message *msg = host->cur_msg;
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struct spi_engine *spi_engine = spi_controller_get_devdata(host);
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unsigned int disable_int = 0;
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unsigned int pending;
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int completed_id = -1;
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pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
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if (pending & SPI_ENGINE_INT_SYNC) {
|
|
writel_relaxed(SPI_ENGINE_INT_SYNC,
|
|
spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
|
completed_id = readl_relaxed(
|
|
spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
|
|
}
|
|
|
|
spin_lock(&spi_engine->lock);
|
|
|
|
if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
|
|
if (!spi_engine_write_cmd_fifo(spi_engine, msg))
|
|
disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
|
|
}
|
|
|
|
if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
|
|
if (!spi_engine_write_tx_fifo(spi_engine, msg))
|
|
disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
|
|
}
|
|
|
|
if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
|
|
if (!spi_engine_read_rx_fifo(spi_engine, msg))
|
|
disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
|
|
}
|
|
|
|
if (pending & SPI_ENGINE_INT_SYNC && msg) {
|
|
if (completed_id == AXI_SPI_ENGINE_CUR_MSG_SYNC_ID) {
|
|
msg->status = 0;
|
|
msg->actual_length = msg->frame_length;
|
|
complete(&spi_engine->msg_complete);
|
|
disable_int |= SPI_ENGINE_INT_SYNC;
|
|
}
|
|
}
|
|
|
|
if (disable_int) {
|
|
spi_engine->int_enable &= ~disable_int;
|
|
writel_relaxed(spi_engine->int_enable,
|
|
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
}
|
|
|
|
spin_unlock(&spi_engine->lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int spi_engine_optimize_message(struct spi_message *msg)
|
|
{
|
|
struct spi_engine_program p_dry, *p;
|
|
|
|
spi_engine_precompile_message(msg);
|
|
|
|
p_dry.length = 0;
|
|
spi_engine_compile_message(msg, true, &p_dry);
|
|
|
|
p = kzalloc(struct_size(p, instructions, p_dry.length + 1), GFP_KERNEL);
|
|
if (!p)
|
|
return -ENOMEM;
|
|
|
|
spi_engine_compile_message(msg, false, p);
|
|
|
|
spi_engine_program_add_cmd(p, false, SPI_ENGINE_CMD_SYNC(
|
|
AXI_SPI_ENGINE_CUR_MSG_SYNC_ID));
|
|
|
|
msg->opt_state = p;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_engine_unoptimize_message(struct spi_message *msg)
|
|
{
|
|
kfree(msg->opt_state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_engine_transfer_one_message(struct spi_controller *host,
|
|
struct spi_message *msg)
|
|
{
|
|
struct spi_engine *spi_engine = spi_controller_get_devdata(host);
|
|
struct spi_engine_message_state *st = &spi_engine->msg_state;
|
|
struct spi_engine_program *p = msg->opt_state;
|
|
unsigned int int_enable = 0;
|
|
unsigned long flags;
|
|
|
|
/* reinitialize message state for this transfer */
|
|
memset(st, 0, sizeof(*st));
|
|
st->cmd_buf = p->instructions;
|
|
st->cmd_length = p->length;
|
|
msg->state = st;
|
|
|
|
reinit_completion(&spi_engine->msg_complete);
|
|
|
|
spin_lock_irqsave(&spi_engine->lock, flags);
|
|
|
|
if (spi_engine_write_cmd_fifo(spi_engine, msg))
|
|
int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
|
|
|
|
spi_engine_tx_next(msg);
|
|
if (spi_engine_write_tx_fifo(spi_engine, msg))
|
|
int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
|
|
|
|
spi_engine_rx_next(msg);
|
|
if (st->rx_length != 0)
|
|
int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
|
|
|
|
int_enable |= SPI_ENGINE_INT_SYNC;
|
|
|
|
writel_relaxed(int_enable,
|
|
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
spi_engine->int_enable = int_enable;
|
|
spin_unlock_irqrestore(&spi_engine->lock, flags);
|
|
|
|
if (!wait_for_completion_timeout(&spi_engine->msg_complete,
|
|
msecs_to_jiffies(5000))) {
|
|
dev_err(&host->dev,
|
|
"Timeout occurred while waiting for transfer to complete. Hardware is probably broken.\n");
|
|
msg->status = -ETIMEDOUT;
|
|
}
|
|
|
|
spi_finalize_current_message(host);
|
|
|
|
return msg->status;
|
|
}
|
|
|
|
static void spi_engine_release_hw(void *p)
|
|
{
|
|
struct spi_engine *spi_engine = p;
|
|
|
|
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
|
|
}
|
|
|
|
static int spi_engine_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_engine *spi_engine;
|
|
struct spi_controller *host;
|
|
unsigned int version;
|
|
int irq;
|
|
int ret;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi_engine));
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
spi_engine = spi_controller_get_devdata(host);
|
|
|
|
spin_lock_init(&spi_engine->lock);
|
|
init_completion(&spi_engine->msg_complete);
|
|
|
|
spi_engine->clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
|
|
if (IS_ERR(spi_engine->clk))
|
|
return PTR_ERR(spi_engine->clk);
|
|
|
|
spi_engine->ref_clk = devm_clk_get_enabled(&pdev->dev, "spi_clk");
|
|
if (IS_ERR(spi_engine->ref_clk))
|
|
return PTR_ERR(spi_engine->ref_clk);
|
|
|
|
spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(spi_engine->base))
|
|
return PTR_ERR(spi_engine->base);
|
|
|
|
version = readl(spi_engine->base + ADI_AXI_REG_VERSION);
|
|
if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) {
|
|
dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
|
|
ADI_AXI_PCORE_VER_MAJOR(version),
|
|
ADI_AXI_PCORE_VER_MINOR(version),
|
|
ADI_AXI_PCORE_VER_PATCH(version));
|
|
return -ENODEV;
|
|
}
|
|
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
|
|
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
|
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
|
|
|
ret = devm_add_action_or_reset(&pdev->dev, spi_engine_release_hw,
|
|
spi_engine);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, spi_engine_irq, 0, pdev->name,
|
|
host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
host->dev.of_node = pdev->dev.of_node;
|
|
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
|
|
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
|
host->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
|
|
host->transfer_one_message = spi_engine_transfer_one_message;
|
|
host->optimize_message = spi_engine_optimize_message;
|
|
host->unoptimize_message = spi_engine_unoptimize_message;
|
|
host->num_chipselect = 8;
|
|
|
|
if (host->max_speed_hz == 0)
|
|
return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");
|
|
|
|
ret = devm_spi_register_controller(&pdev->dev, host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id spi_engine_match_table[] = {
|
|
{ .compatible = "adi,axi-spi-engine-1.00.a" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spi_engine_match_table);
|
|
|
|
static struct platform_driver spi_engine_driver = {
|
|
.probe = spi_engine_probe,
|
|
.driver = {
|
|
.name = "spi-engine",
|
|
.of_match_table = spi_engine_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(spi_engine_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
|
|
MODULE_LICENSE("GPL");
|