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8233a0dee9
Add DMA properties to all SCIF, SCIFA, SCIFB, and HSCIF device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
779 lines
22 KiB
Plaintext
779 lines
22 KiB
Plaintext
/*
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* Device Tree Source for the r8a7794 SoC
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7794-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7794";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clock-frequency = <1000000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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clock-frequency = <1000000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
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clock-names = "fck";
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 126 IRQ_TYPE_LEVEL_HIGH>,
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<0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7794", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
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0 200 IRQ_TYPE_LEVEL_HIGH
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0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH
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0 205 IRQ_TYPE_LEVEL_HIGH
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0 206 IRQ_TYPE_LEVEL_HIGH
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0 207 IRQ_TYPE_LEVEL_HIGH
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0 208 IRQ_TYPE_LEVEL_HIGH
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0 209 IRQ_TYPE_LEVEL_HIGH
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0 210 IRQ_TYPE_LEVEL_HIGH
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0 211 IRQ_TYPE_LEVEL_HIGH
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0 212 IRQ_TYPE_LEVEL_HIGH
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0 213 IRQ_TYPE_LEVEL_HIGH
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0 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
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0 216 IRQ_TYPE_LEVEL_HIGH
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0 217 IRQ_TYPE_LEVEL_HIGH
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0 218 IRQ_TYPE_LEVEL_HIGH
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0 219 IRQ_TYPE_LEVEL_HIGH
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0 308 IRQ_TYPE_LEVEL_HIGH
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0 309 IRQ_TYPE_LEVEL_HIGH
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0 310 IRQ_TYPE_LEVEL_HIGH
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0 311 IRQ_TYPE_LEVEL_HIGH
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0 312 IRQ_TYPE_LEVEL_HIGH
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0 313 IRQ_TYPE_LEVEL_HIGH
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0 314 IRQ_TYPE_LEVEL_HIGH
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0 315 IRQ_TYPE_LEVEL_HIGH
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0 316 IRQ_TYPE_LEVEL_HIGH
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0 317 IRQ_TYPE_LEVEL_HIGH
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0 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x21>, <&dmac0 0x22>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x25>, <&dmac0 0x26>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c60000 0 64>;
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interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x27>, <&dmac0 0x28>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c70000 0 64>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifa4: serial@e6c78000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c78000 0 64>;
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interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifa5: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7794", "renesas,scifa";
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reg = <0 0xe6c80000 0 64>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x23>, <&dmac0 0x24>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifb0: serial@e6c20000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6c20000 0 64>;
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interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifb1: serial@e6c30000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6c30000 0 64>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scifb2: serial@e6ce0000 {
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compatible = "renesas,scifb-r8a7794", "renesas,scifb";
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reg = <0 0xe6ce0000 0 64>;
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interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif2: serial@e6e58000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6e58000 0 64>;
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interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif3: serial@e6ea8000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ea8000 0 64>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif4: serial@e6ee0000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ee0000 0 64>;
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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scif5: serial@e6ee8000 {
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compatible = "renesas,scif-r8a7794", "renesas,scif";
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reg = <0 0xe6ee8000 0 64>;
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interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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hscif0: serial@e62c0000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62c0000 0 96>;
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interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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hscif1: serial@e62c8000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62c8000 0 96>;
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interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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hscif2: serial@e62d0000 {
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compatible = "renesas,hscif-r8a7794", "renesas,hscif";
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reg = <0 0xe62d0000 0 96>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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ether: ethernet@ee700000 {
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compatible = "renesas,ether-r8a7794";
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reg = <0 0xee700000 0 0x400>;
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interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
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phy-mode = "rmii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sdhi0: sd@ee100000 {
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compatible = "renesas,sdhi-r8a7794";
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reg = <0 0xee100000 0 0x200>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
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status = "disabled";
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};
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sdhi1: sd@ee140000 {
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compatible = "renesas,sdhi-r8a7794";
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reg = <0 0xee140000 0 0x100>;
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interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
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status = "disabled";
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};
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sdhi2: sd@ee160000 {
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compatible = "renesas,sdhi-r8a7794";
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reg = <0 0xee160000 0 0x100>;
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interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
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status = "disabled";
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7794-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
"lb", "qspi", "sdh", "sd0", "z";
|
|
};
|
|
/* Variable factor clocks */
|
|
sd2_clk: sd2_clk@e6150078 {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150078 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd2";
|
|
};
|
|
sd3_clk: sd3_clk@e615026c {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615026c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd3";
|
|
};
|
|
mmc0_clk: mmc0_clk@e6150240 {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150240 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mmc0";
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
pll1_div2_clk: pll1_div2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "pll1_div2";
|
|
};
|
|
zg_clk: zg_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zg";
|
|
};
|
|
zx_clk: zx_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zx";
|
|
};
|
|
zs_clk: zs_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zs";
|
|
};
|
|
hp_clk: hp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "hp";
|
|
};
|
|
i_clk: i_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "i";
|
|
};
|
|
b_clk: b_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "b";
|
|
};
|
|
p_clk: p_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "p";
|
|
};
|
|
cl_clk: cl_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cl";
|
|
};
|
|
m2_clk: m2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "m2";
|
|
};
|
|
imp_clk: imp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "imp";
|
|
};
|
|
rclk_clk: rclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(48 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "rclk";
|
|
};
|
|
oscclk_clk: oscclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(12 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "oscclk";
|
|
};
|
|
zb3_clk: zb3_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3";
|
|
};
|
|
zb3d2_clk: zb3d2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3d2";
|
|
};
|
|
ddr_clk: ddr_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "ddr";
|
|
};
|
|
mp_clk: mp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <15>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "mp";
|
|
};
|
|
cp_clk: cp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cp";
|
|
};
|
|
|
|
acp_clk: acp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "acp";
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
|
clocks = <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_MSIOF0>;
|
|
clock-output-names = "msiof0";
|
|
};
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
|
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
|
|
<&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
|
|
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
|
|
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
|
|
R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
|
|
>;
|
|
clock-output-names =
|
|
"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
|
|
"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
|
|
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
|
|
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
|
|
R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
|
|
>;
|
|
clock-output-names =
|
|
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
|
"scifb1", "msiof1", "scifb2",
|
|
"sys-dmac1", "sys-dmac0";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
|
clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
|
|
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
|
|
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
|
|
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
|
|
>;
|
|
clock-output-names =
|
|
"sdhi2", "sdhi1", "sdhi0",
|
|
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
|
|
};
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
|
|
clocks = <&cp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_IRQC>;
|
|
clock-output-names = "irqc";
|
|
};
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
|
|
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
|
|
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
|
|
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
|
|
R8A7794_CLK_SCIF0
|
|
>;
|
|
clock-output-names =
|
|
"ehci", "hsusb",
|
|
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
|
"scif3", "scif2", "scif1", "scif0";
|
|
};
|
|
mstp8_clks: mstp8_clks@e6150990 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
|
clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
|
|
>;
|
|
clock-output-names =
|
|
"vin1", "vin0", "ether";
|
|
};
|
|
mstp9_clks: mstp9_clks@e6150994 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
|
clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
|
|
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
|
|
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
|
|
R8A7794_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
|
};
|
|
mstp11_clks: mstp11_clks@e615099c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
|
|
>;
|
|
clock-output-names = "scifa3", "scifa4", "scifa5";
|
|
};
|
|
};
|
|
|
|
ipmmu_sy0: mmu@e6280000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6280000 0 0x1000>;
|
|
interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_sy1: mmu@e6290000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6290000 0 0x1000>;
|
|
interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_ds: mmu@e6740000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6740000 0 0x1000>;
|
|
interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mp: mmu@ec680000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xec680000 0 0x1000>;
|
|
interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_mx: mmu@fe951000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xfe951000 0 0x1000>;
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_gp: mmu@e62a0000 {
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe62a0000 0 0x1000>;
|
|
interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 261 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|