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8c91c5325e
Similar to:
2ca052a x86: Use correct byte-sized register constraint in __xchg_op()
... the __add() macro also needs to use a "q" constraint in the
byte-sized case, lest we try to generate an illegal register.
Link: http://lkml.kernel.org/r/4F7A3315.501@goop.org
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Leigh Scott <leigh123linux@googlemail.com>
Cc: Thomas Reitmayr <treitmayr@devbase.at>
Cc: <stable@vger.kernel.org> v3.3
234 lines
6.9 KiB
C
234 lines
6.9 KiB
C
#ifndef ASM_X86_CMPXCHG_H
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#define ASM_X86_CMPXCHG_H
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#include <linux/compiler.h>
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#include <asm/alternative.h> /* Provides LOCK_PREFIX */
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/*
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* Non-existant functions to indicate usage errors at link time
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* (or compile-time if the compiler implements __compiletime_error().
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*/
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extern void __xchg_wrong_size(void)
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__compiletime_error("Bad argument size for xchg");
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extern void __cmpxchg_wrong_size(void)
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__compiletime_error("Bad argument size for cmpxchg");
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extern void __xadd_wrong_size(void)
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__compiletime_error("Bad argument size for xadd");
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extern void __add_wrong_size(void)
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__compiletime_error("Bad argument size for add");
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/*
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* Constants for operation sizes. On 32-bit, the 64-bit size it set to
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* -1 because sizeof will never return -1, thereby making those switch
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* case statements guaranteeed dead code which the compiler will
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* eliminate, and allowing the "missing symbol in the default case" to
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* indicate a usage error.
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*/
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#define __X86_CASE_B 1
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#define __X86_CASE_W 2
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#define __X86_CASE_L 4
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#ifdef CONFIG_64BIT
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#define __X86_CASE_Q 8
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#else
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#define __X86_CASE_Q -1 /* sizeof will never return -1 */
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#endif
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/*
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* An exchange-type operation, which takes a value and a pointer, and
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* returns a the old value.
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*/
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#define __xchg_op(ptr, arg, op, lock) \
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({ \
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__typeof__ (*(ptr)) __ret = (arg); \
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switch (sizeof(*(ptr))) { \
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case __X86_CASE_B: \
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asm volatile (lock #op "b %b0, %1\n" \
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: "+q" (__ret), "+m" (*(ptr)) \
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: : "memory", "cc"); \
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break; \
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case __X86_CASE_W: \
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asm volatile (lock #op "w %w0, %1\n" \
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: "+r" (__ret), "+m" (*(ptr)) \
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: : "memory", "cc"); \
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break; \
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case __X86_CASE_L: \
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asm volatile (lock #op "l %0, %1\n" \
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: "+r" (__ret), "+m" (*(ptr)) \
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: : "memory", "cc"); \
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break; \
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case __X86_CASE_Q: \
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asm volatile (lock #op "q %q0, %1\n" \
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: "+r" (__ret), "+m" (*(ptr)) \
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: : "memory", "cc"); \
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break; \
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default: \
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__ ## op ## _wrong_size(); \
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} \
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__ret; \
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})
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
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* Since this is generally used to protect other memory information, we
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* use "asm volatile" and "memory" clobbers to prevent gcc from moving
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* information around.
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*/
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#define xchg(ptr, v) __xchg_op((ptr), (v), xchg, "")
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __raw_cmpxchg(ptr, old, new, size, lock) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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switch (size) { \
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case __X86_CASE_B: \
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{ \
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volatile u8 *__ptr = (volatile u8 *)(ptr); \
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asm volatile(lock "cmpxchgb %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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: "q" (__new), "0" (__old) \
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: "memory"); \
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break; \
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} \
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case __X86_CASE_W: \
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{ \
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volatile u16 *__ptr = (volatile u16 *)(ptr); \
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asm volatile(lock "cmpxchgw %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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: "r" (__new), "0" (__old) \
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: "memory"); \
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break; \
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} \
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case __X86_CASE_L: \
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{ \
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volatile u32 *__ptr = (volatile u32 *)(ptr); \
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asm volatile(lock "cmpxchgl %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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: "r" (__new), "0" (__old) \
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: "memory"); \
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break; \
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} \
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case __X86_CASE_Q: \
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{ \
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volatile u64 *__ptr = (volatile u64 *)(ptr); \
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asm volatile(lock "cmpxchgq %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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: "r" (__new), "0" (__old) \
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: "memory"); \
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break; \
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} \
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default: \
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__cmpxchg_wrong_size(); \
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} \
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__ret; \
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})
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#define __cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
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#define __sync_cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
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#define __cmpxchg_local(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "")
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#ifdef CONFIG_X86_32
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# include "cmpxchg_32.h"
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#else
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# include "cmpxchg_64.h"
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#endif
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#ifdef __HAVE_ARCH_CMPXCHG
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#define cmpxchg(ptr, old, new) \
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__cmpxchg(ptr, old, new, sizeof(*(ptr)))
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#define sync_cmpxchg(ptr, old, new) \
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__sync_cmpxchg(ptr, old, new, sizeof(*(ptr)))
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#define cmpxchg_local(ptr, old, new) \
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__cmpxchg_local(ptr, old, new, sizeof(*(ptr)))
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#endif
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/*
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* xadd() adds "inc" to "*ptr" and atomically returns the previous
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* value of "*ptr".
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*
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* xadd() is locked when multiple CPUs are online
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* xadd_sync() is always locked
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* xadd_local() is never locked
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*/
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#define __xadd(ptr, inc, lock) __xchg_op((ptr), (inc), xadd, lock)
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#define xadd(ptr, inc) __xadd((ptr), (inc), LOCK_PREFIX)
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#define xadd_sync(ptr, inc) __xadd((ptr), (inc), "lock; ")
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#define xadd_local(ptr, inc) __xadd((ptr), (inc), "")
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#define __add(ptr, inc, lock) \
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({ \
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__typeof__ (*(ptr)) __ret = (inc); \
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switch (sizeof(*(ptr))) { \
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case __X86_CASE_B: \
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asm volatile (lock "addb %b1, %0\n" \
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: "+m" (*(ptr)) : "qi" (inc) \
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: "memory", "cc"); \
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break; \
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case __X86_CASE_W: \
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asm volatile (lock "addw %w1, %0\n" \
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: "+m" (*(ptr)) : "ri" (inc) \
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: "memory", "cc"); \
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break; \
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case __X86_CASE_L: \
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asm volatile (lock "addl %1, %0\n" \
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: "+m" (*(ptr)) : "ri" (inc) \
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: "memory", "cc"); \
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break; \
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case __X86_CASE_Q: \
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asm volatile (lock "addq %1, %0\n" \
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: "+m" (*(ptr)) : "ri" (inc) \
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: "memory", "cc"); \
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break; \
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default: \
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__add_wrong_size(); \
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} \
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__ret; \
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})
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/*
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* add_*() adds "inc" to "*ptr"
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*
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* __add() takes a lock prefix
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* add_smp() is locked when multiple CPUs are online
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* add_sync() is always locked
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*/
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#define add_smp(ptr, inc) __add((ptr), (inc), LOCK_PREFIX)
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#define add_sync(ptr, inc) __add((ptr), (inc), "lock; ")
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#define __cmpxchg_double(pfx, p1, p2, o1, o2, n1, n2) \
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({ \
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bool __ret; \
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__typeof__(*(p1)) __old1 = (o1), __new1 = (n1); \
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__typeof__(*(p2)) __old2 = (o2), __new2 = (n2); \
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BUILD_BUG_ON(sizeof(*(p1)) != sizeof(long)); \
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BUILD_BUG_ON(sizeof(*(p2)) != sizeof(long)); \
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VM_BUG_ON((unsigned long)(p1) % (2 * sizeof(long))); \
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VM_BUG_ON((unsigned long)((p1) + 1) != (unsigned long)(p2)); \
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asm volatile(pfx "cmpxchg%c4b %2; sete %0" \
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: "=a" (__ret), "+d" (__old2), \
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"+m" (*(p1)), "+m" (*(p2)) \
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: "i" (2 * sizeof(long)), "a" (__old1), \
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"b" (__new1), "c" (__new2)); \
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__ret; \
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})
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#define cmpxchg_double(p1, p2, o1, o2, n1, n2) \
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__cmpxchg_double(LOCK_PREFIX, p1, p2, o1, o2, n1, n2)
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#define cmpxchg_double_local(p1, p2, o1, o2, n1, n2) \
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__cmpxchg_double(, p1, p2, o1, o2, n1, n2)
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#endif /* ASM_X86_CMPXCHG_H */
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