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249bb070f5
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
251 lines
6.2 KiB
C
251 lines
6.2 KiB
C
/*
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* OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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*
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* [ Initialisation is based on Linus' ]
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* [ uhci code and gregs ohci fragments ]
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* [ (C) Copyright 1999 Linus Torvalds ]
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* [ (C) Copyright 1999 Gregory P. Smith]
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*
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* PCI Bus Glue
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*
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* This file is licenced under the GPL.
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*/
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#include <linux/jiffies.h>
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#ifdef CONFIG_PPC_PMAC
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/pci-bridge.h>
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#include <asm/prom.h>
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#endif
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#ifndef CONFIG_PCI
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#error "This file is PCI bus glue. CONFIG_PCI must be defined."
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#endif
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/*-------------------------------------------------------------------------*/
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static int
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ohci_pci_reset (struct usb_hcd *hcd)
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{
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struct ohci_hcd *ohci = hcd_to_ohci (hcd);
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ohci_hcd_init (ohci);
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return ohci_init (ohci);
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}
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static int __devinit
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ohci_pci_start (struct usb_hcd *hcd)
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{
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struct ohci_hcd *ohci = hcd_to_ohci (hcd);
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int ret;
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if(hcd->self.controller && hcd->self.controller->bus == &pci_bus_type) {
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/* AMD 756, for most chips (early revs), corrupts register
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* values on read ... so enable the vendor workaround.
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*/
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if (pdev->vendor == PCI_VENDOR_ID_AMD
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&& pdev->device == 0x740c) {
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ohci->flags = OHCI_QUIRK_AMD756;
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ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
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// also somewhat erratum 10 (suspend/resume issues)
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}
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/* FIXME for some of the early AMD 760 southbridges, OHCI
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* won't work at all. blacklist them.
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*/
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/* Apple's OHCI driver has a lot of bizarre workarounds
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* for this chip. Evidently control and bulk lists
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* can get confused. (B&W G3 models, and ...)
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*/
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else if (pdev->vendor == PCI_VENDOR_ID_OPTI
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&& pdev->device == 0xc861) {
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ohci_dbg (ohci,
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"WARNING: OPTi workarounds unavailable\n");
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}
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/* Check for NSC87560. We have to look at the bridge (fn1) to
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* identify the USB (fn2). This quirk might apply to more or
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* even all NSC stuff.
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*/
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else if (pdev->vendor == PCI_VENDOR_ID_NS) {
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struct pci_dev *b;
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b = pci_find_slot (pdev->bus->number,
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PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
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if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
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&& b->vendor == PCI_VENDOR_ID_NS) {
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ohci->flags |= OHCI_QUIRK_SUPERIO;
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ohci_dbg (ohci, "Using NSC SuperIO setup\n");
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}
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}
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/* Check for Compaq's ZFMicro chipset, which needs short
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* delays before control or bulk queues get re-activated
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* in finish_unlinks()
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*/
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else if (pdev->vendor == PCI_VENDOR_ID_COMPAQ
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&& pdev->device == 0xa0f8) {
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ohci->flags |= OHCI_QUIRK_ZFMICRO;
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ohci_dbg (ohci,
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"enabled Compaq ZFMicro chipset quirk\n");
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}
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}
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/* NOTE: there may have already been a first reset, to
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* keep bios/smm irqs from making trouble
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*/
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if ((ret = ohci_run (ohci)) < 0) {
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ohci_err (ohci, "can't start\n");
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ohci_stop (hcd);
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return ret;
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}
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return 0;
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}
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#ifdef CONFIG_PM
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static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
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{
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/* root hub was already suspended */
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/* FIXME these PMAC things get called in the wrong places. ASIC
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* clocks should be turned off AFTER entering D3, and on BEFORE
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* trying to enter D0. Evidently the PCI layer doesn't currently
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* provide the right sort of platform hooks for this ...
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*/
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#ifdef CONFIG_PPC_PMAC
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if (_machine == _MACH_Pmac) {
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struct device_node *of_node;
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/* Disable USB PAD & cell clock */
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of_node = pci_device_to_OF_node (to_pci_dev(hcd->self.controller));
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if (of_node)
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pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 0);
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}
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#endif /* CONFIG_PPC_PMAC */
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return 0;
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}
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static int ohci_pci_resume (struct usb_hcd *hcd)
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{
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#ifdef CONFIG_PPC_PMAC
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if (_machine == _MACH_Pmac) {
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struct device_node *of_node;
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/* Re-enable USB PAD & cell clock */
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of_node = pci_device_to_OF_node (to_pci_dev(hcd->self.controller));
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if (of_node)
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pmac_call_feature (PMAC_FTR_USB_ENABLE, of_node, 0, 1);
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}
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#endif /* CONFIG_PPC_PMAC */
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usb_hcd_resume_root_hub(hcd);
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return 0;
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}
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#endif /* CONFIG_PM */
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/*-------------------------------------------------------------------------*/
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static const struct hc_driver ohci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "OHCI Host Controller",
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.hcd_priv_size = sizeof(struct ohci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ohci_irq,
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.flags = HCD_MEMORY | HCD_USB11,
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/*
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* basic lifecycle operations
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*/
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.reset = ohci_pci_reset,
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.start = ohci_pci_start,
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#ifdef CONFIG_PM
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.suspend = ohci_pci_suspend,
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.resume = ohci_pci_resume,
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#endif
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.stop = ohci_stop,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ohci_urb_enqueue,
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.urb_dequeue = ohci_urb_dequeue,
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.endpoint_disable = ohci_endpoint_disable,
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/*
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* scheduling support
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*/
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.get_frame_number = ohci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ohci_hub_status_data,
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.hub_control = ohci_hub_control,
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#ifdef CONFIG_PM
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.bus_suspend = ohci_bus_suspend,
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.bus_resume = ohci_bus_resume,
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#endif
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.start_port_reset = ohci_start_port_reset,
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};
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/*-------------------------------------------------------------------------*/
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static const struct pci_device_id pci_ids [] = { {
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/* handle any USB OHCI controller */
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PCI_DEVICE_CLASS((PCI_CLASS_SERIAL_USB << 8) | 0x10, ~0),
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.driver_data = (unsigned long) &ohci_pci_hc_driver,
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}, { /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE (pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ohci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = usb_hcd_pci_probe,
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.remove = usb_hcd_pci_remove,
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#ifdef CONFIG_PM
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.suspend = usb_hcd_pci_suspend,
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.resume = usb_hcd_pci_resume,
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#endif
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};
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static int __init ohci_hcd_pci_init (void)
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{
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printk (KERN_DEBUG "%s: " DRIVER_INFO " (PCI)\n", hcd_name);
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if (usb_disabled())
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return -ENODEV;
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pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
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sizeof (struct ed), sizeof (struct td));
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return pci_register_driver (&ohci_pci_driver);
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}
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module_init (ohci_hcd_pci_init);
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/*-------------------------------------------------------------------------*/
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static void __exit ohci_hcd_pci_cleanup (void)
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{
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pci_unregister_driver (&ohci_pci_driver);
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}
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module_exit (ohci_hcd_pci_cleanup);
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