Andre Przywara b45c6d8032 phy: sun4i-usb: Introduce port2 SIDDQ quirk ... At least the Allwinner H616 SoC requires a weird quirk to make most USB PHYs work: Only port2 works out of the box, but all other ports need some help from this port2 to work correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in the PMU PHY control register needs to be cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... Instead of disguising this as some generic feature, treat it more like a quirk (what it really is): If the quirk bit is set, and we initialise a PHY other than PHY2, ungate this one special clock, and clear the SIDDQ bit. We also pick the clock and reset from PHY2 and enable them as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20221031111358.3387297-4-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-11-07 10:20:25 +05:30
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Kconfig	phy: allwinner: Make PHY_SUN6I_MIPI_DPHY depend on COMMON_CLK	2020-07-13 10:40:53 +05:30
Makefile	phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC	2019-10-31 16:54:00 +05:30
phy-sun4i-usb.c	phy: sun4i-usb: Introduce port2 SIDDQ quirk	2022-11-07 10:20:25 +05:30
phy-sun6i-mipi-dphy.c	phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2	2022-04-20 14:40:12 +05:30
phy-sun9i-usb.c	phy: allwinner: convert to devm_platform_ioremap_resource(_byname)	2020-11-16 12:47:46 +05:30
phy-sun50i-usb3.c	phy: allwinner: convert to devm_platform_ioremap_resource(_byname)	2020-11-16 12:47:46 +05:30