Arnd Bergmann b453988c59 RISC-V Devicetrees for v6.3-mw0 ... Microchip: A vendor prefix for Aldec and both a binding and Devicetree for the Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to what they are shipping in the SDK for rev2 boards. StarFive: Just the binding for the new StarFive JH7110 SoC and its first-party SDC the VisionFive 2. Other: I was expecting the Devicetree for the aforementioned board to be ready for this window, as the pinctrl driver had seem some review prior to v6.2 and both it & the base clock drivers are heavily based on the existing drivers for the JH7110. That didn't come to be.. Christmas, the RISC-V Summit in December and the Lunar New Year all playing a part perhaps. Because of that, both Palmer and I have the Kconfig.socs work in our branches, although in hindsight it probably wasn't needed here as I only added the TySoM Devicetree & the conflict would've been trivial. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9EPgwAKCRB4tDGHoIJi 0l9kAQDJHyrjfXMooRHSFXRUsJFYeN8MpYvD1CLavdrD+Pu+KQD/c1sApjfZrKjo ItyEL37F2QJOAFY1rAxdB7d6ppsUEAQ= =sN4y -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPX9PcACgkQmmx57+YA GNn4Xg/+MykVFbZuQZbFuzD9DNA3BnHJuJL+5Uz1Ywy9H+Katl4hQGRLlt4WtRzC fWuteoPmNwvsbxuDRQ3sDC2oqRFVFD45u/q7qQ4ce+dKDbL2qpnbgxdmXVXdJrgL e9Wb9V01j8vLimNvFspicnaajFwDEC1uGLbVaZ+RKEk6GxxlJEJqydUsa2FVbQIf QDMEtR967fI3CUZ2wvzplJDDGBBKZbXxuZ/tOaTwEGPKFxbzQ5CBP7CFkbfEEjTZ kbcHsfLloKLL1/11oBeR6aPhY1WQvecBHO9WZ3ANR+/+2GT9SLdPbCWQN+uWM9ZI B5/SvtvJhzyP6HG+ErX/Pc8NPjm6AKMoo6j8fLuy8pASJF+H3tV9bn9mj4ld6B1S Vz8D1/hoh7OIuEaRDdfzW8xHQS6qQF58MRS3J8+I3xTUs4ZP6JifnOdIcrbXYvup +SFRgtoewV4wMxPshM+5FsVqsE4xSnvdwZeuxIjqpFY/CvlubFJdT9FBx8tx+v+G rC7MtoggznsQi1BDShGbu0xNAmE6iJcv9mranFm6NQUXC5/1SObIA9RFb0aBBJoQ DsU1rDqWndh9bILZkoikpPQ0uZWwAOFRpp44CSZ6/YtYPDku99YWozxqCeGGw4gN V18SjBXgL9YZfQKH3Z0biOdv6m2vLJKoj5hxgzu0KFxbCFlrl+A= =SCZP -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/dt RISC-V Devicetrees for v6.3-mw0 Microchip: A vendor prefix for Aldec and both a binding and Devicetree for the Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to what they are shipping in the SDK for rev2 boards. StarFive: Just the binding for the new StarFive JH7110 SoC and its first-party SDC the VisionFive 2. Other: I was expecting the Devicetree for the aforementioned board to be ready for this window, as the pinctrl driver had seem some review prior to v6.2 and both it & the base clock drivers are heavily based on the existing drivers for the JH7110. That didn't come to be.. Christmas, the RISC-V Summit in December and the Lunar New Year all playing a part perhaps. Because of that, both Palmer and I have the Kconfig.socs work in our branches, although in hindsight it probably wasn't needed here as I only added the TySoM Devicetree & the conflict would've been trivial. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: microchip: add the Aldec TySoM's devicetree dt-bindings: riscv: microchip: document the Aldec TySoM dt-bindings: vendor-prefixes: Add entry for Aldec RISC-V: stop directly selecting drivers for SOC_CANAAN RISC-V: stop selecting SiFive clock and serial drivers directly RISC-V: stop selecting the PolarFire SoC clock driver RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Link: https://lore.kernel.org/r/Y9LP+Za1h0fkBa58@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>		2023-01-30 17:48:55 +01:00
..
boot	RISC-V Devicetrees for v6.3-mw0	2023-01-30 17:48:55 +01:00
configs	RISC-V Patches for the 6.2 Merge Window, Part 1	2022-12-14 15:23:49 -08:00
errata	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2022-10-27 14:35:20 -07:00
include	riscv: uaccess: fix type of 0 variable on error in get_user()	2023-01-05 12:30:41 -08:00
kernel	riscv, kprobes: Stricter c.jr/c.jalr decoding	2023-01-05 12:30:41 -08:00
kvm	RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid	2022-12-07 09:17:49 +05:30
lib	riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit	2022-08-10 14:06:31 -07:00
mm	RISC-V Patches for the 6.2 Merge Window, Part 1	2022-12-14 15:23:49 -08:00
net	riscv, bpf: Emit fixed-length instructions for BPF_PSEUDO_FUNC	2022-12-06 20:59:27 +01:00
purgatory	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	RISC-V Patches for the 6.2 Merge Window, Part 1	2022-12-14 15:23:49 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2022-10-27 14:35:20 -07:00
Kconfig.socs	RISC-V: stop directly selecting drivers for SOC_CANAAN	2022-12-27 18:01:40 +00:00
Makefile	RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO	2022-12-27 18:01:40 +00:00