mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-23 11:04:44 +08:00
93b694d096
New driver: Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJfh579AAoJEAx081l5xIa+GqoP/0amz+ZN7y/L7+f32CRinJ7/ 3e4xjXNDmtWG4Whe/WKjlYmbAcvSdWV/4HYpurW2BFJnOAB/5lIqYcS/PyqErPzA w4EpRoJ+ZdFgmlDH0vdsDwPLT/HFmhUN9AopNkoZpbSMxrManSj5QgmePXyiKReP Q+ZAK5UW5AdOVY4bgXUSEkVq2eilCLXf+bSBR/LrVQuNgu7GULX8SIy/Y1CuMtv8 LgzzjLKfIZaIWC+F/RU7BxJ7YnrVq7z7yXnUx8j2416+k/Wwe+BeSUCSZstT7q9G UkX8jWfR7ZKqhwP+UQeSwDbHkALz7lv88nyjQdxJZ3SrXRe4hy14YjxnR4maeNAj 3TAYSdcAMWyRHqeEZIZ7Hj5sQtTq5OZAoIjxzH3vpVdAnnAkcWoF77pqxV8XPqTC nw40DihAxQOshGwMkjd5DqkEwnMv43Hs1WTVYu9dPTOfOdqPNt+Vqp7Xl9Z46+kV k6PDcx60T9ayDW1QZ6MoIXHta9E7ixzu7gYBL3vP4LuporY0uNG3bzF3CMvof1BK sHYcYTdZkqbTD2d6rHV+TbpPQXgTtlej9qVlQM4SeX37Xtc7LxCYpnpUHKz2S/fK 1vyeGPgdytHblwlxwZOPZ4R2I/HTfnITdr4kMcJHhxAsEewfW1Rd4+stQqVJ2Mph Vz+CFP2BngivGFz5vuky =4H8J -----END PGP SIGNATURE----- Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Not a major amount of change, the i915 trees got split into display and gt trees to better facilitate higher level review, and there's a major refactoring of i915 GEM locking to use more core kernel concepts (like ww-mutexes). msm gets per-process pagetables, older AMD SI cards get DC support, nouveau got a bump in displayport support with common code extraction from i915. Outside of drm this contains a couple of patches for hexint moduleparams which you've acked, and a virtio common code tree that you should also get via it's regular path. New driver: - Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config" * tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits) drm/ingenic: Fix bad revert drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init drm/amdgpu: Remove warning for virtual_display drm/amdgpu: kfd_initialized can be static drm/amd/pm: setup APU dpm clock table in SMU HW initialization drm/amdgpu: prevent spurious warning drm/amdgpu/swsmu: fix ARC build errors drm/amd/display: Fix OPTC_DATA_FORMAT programming drm/amd/display: Don't allow pstate if no support in blank drm/panfrost: increase readl_relaxed_poll_timeout values MAINTAINERS: Update entry for st7703 driver after the rename Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached" drm/amd/display: HDMI remote sink need mode validation for Linux drm/amd/display: Change to correct unit on audio rate drm/amd/display: Avoid set zero in the requested clk drm/amdgpu: align frag_end to covered address space drm/amdgpu: fix NULL pointer dereference for Renoir drm/vmwgfx: fix regression in thp code due to ttm init refactor. drm/amdgpu/swsmu: add interrupt work handler for smu11 parts drm/amdgpu/swsmu: add interrupt work function ...
705 lines
18 KiB
C
705 lines
18 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nouveau_dmem.h"
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#include "nouveau_drv.h"
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#include "nouveau_chan.h"
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#include "nouveau_dma.h"
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#include "nouveau_mem.h"
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#include "nouveau_bo.h"
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#include "nouveau_svm.h"
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#include <nvif/class.h>
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#include <nvif/object.h>
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#include <nvif/push906f.h>
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#include <nvif/if000c.h>
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#include <nvif/if500b.h>
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#include <nvif/if900b.h>
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#include <nvif/if000c.h>
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#include <nvhw/class/cla0b5.h>
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#include <linux/sched/mm.h>
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#include <linux/hmm.h>
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/*
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* FIXME: this is ugly right now we are using TTM to allocate vram and we pin
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* it in vram while in use. We likely want to overhaul memory management for
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* nouveau to be more page like (not necessarily with system page size but a
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* bigger page size) at lowest level and have some shim layer on top that would
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* provide the same functionality as TTM.
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*/
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#define DMEM_CHUNK_SIZE (2UL << 20)
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#define DMEM_CHUNK_NPAGES (DMEM_CHUNK_SIZE >> PAGE_SHIFT)
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enum nouveau_aper {
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NOUVEAU_APER_VIRT,
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NOUVEAU_APER_VRAM,
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NOUVEAU_APER_HOST,
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};
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typedef int (*nouveau_migrate_copy_t)(struct nouveau_drm *drm, u64 npages,
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enum nouveau_aper, u64 dst_addr,
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enum nouveau_aper, u64 src_addr);
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typedef int (*nouveau_clear_page_t)(struct nouveau_drm *drm, u32 length,
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enum nouveau_aper, u64 dst_addr);
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struct nouveau_dmem_chunk {
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struct list_head list;
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struct nouveau_bo *bo;
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struct nouveau_drm *drm;
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unsigned long callocated;
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struct dev_pagemap pagemap;
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};
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struct nouveau_dmem_migrate {
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nouveau_migrate_copy_t copy_func;
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nouveau_clear_page_t clear_func;
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struct nouveau_channel *chan;
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};
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struct nouveau_dmem {
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struct nouveau_drm *drm;
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struct nouveau_dmem_migrate migrate;
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struct list_head chunks;
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struct mutex mutex;
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struct page *free_pages;
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spinlock_t lock;
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};
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static struct nouveau_dmem_chunk *nouveau_page_to_chunk(struct page *page)
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{
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return container_of(page->pgmap, struct nouveau_dmem_chunk, pagemap);
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}
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static struct nouveau_drm *page_to_drm(struct page *page)
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{
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struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page);
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return chunk->drm;
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}
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unsigned long nouveau_dmem_page_addr(struct page *page)
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{
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struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page);
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unsigned long off = (page_to_pfn(page) << PAGE_SHIFT) -
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chunk->pagemap.range.start;
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return chunk->bo->offset + off;
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}
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static void nouveau_dmem_page_free(struct page *page)
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{
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struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page);
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struct nouveau_dmem *dmem = chunk->drm->dmem;
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spin_lock(&dmem->lock);
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page->zone_device_data = dmem->free_pages;
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dmem->free_pages = page;
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WARN_ON(!chunk->callocated);
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chunk->callocated--;
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/*
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* FIXME when chunk->callocated reach 0 we should add the chunk to
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* a reclaim list so that it can be freed in case of memory pressure.
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*/
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spin_unlock(&dmem->lock);
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}
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static void nouveau_dmem_fence_done(struct nouveau_fence **fence)
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{
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if (fence) {
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nouveau_fence_wait(*fence, true, false);
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nouveau_fence_unref(fence);
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} else {
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/*
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* FIXME wait for channel to be IDLE before calling finalizing
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* the hmem object.
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*/
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}
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}
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static vm_fault_t nouveau_dmem_fault_copy_one(struct nouveau_drm *drm,
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struct vm_fault *vmf, struct migrate_vma *args,
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dma_addr_t *dma_addr)
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{
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struct device *dev = drm->dev->dev;
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struct page *dpage, *spage;
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struct nouveau_svmm *svmm;
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spage = migrate_pfn_to_page(args->src[0]);
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if (!spage || !(args->src[0] & MIGRATE_PFN_MIGRATE))
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return 0;
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dpage = alloc_page_vma(GFP_HIGHUSER, vmf->vma, vmf->address);
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if (!dpage)
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return VM_FAULT_SIGBUS;
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lock_page(dpage);
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*dma_addr = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(dev, *dma_addr))
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goto error_free_page;
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svmm = spage->zone_device_data;
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mutex_lock(&svmm->mutex);
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nouveau_svmm_invalidate(svmm, args->start, args->end);
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if (drm->dmem->migrate.copy_func(drm, 1, NOUVEAU_APER_HOST, *dma_addr,
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NOUVEAU_APER_VRAM, nouveau_dmem_page_addr(spage)))
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goto error_dma_unmap;
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mutex_unlock(&svmm->mutex);
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args->dst[0] = migrate_pfn(page_to_pfn(dpage)) | MIGRATE_PFN_LOCKED;
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return 0;
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error_dma_unmap:
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mutex_unlock(&svmm->mutex);
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dma_unmap_page(dev, *dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
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error_free_page:
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__free_page(dpage);
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return VM_FAULT_SIGBUS;
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}
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static vm_fault_t nouveau_dmem_migrate_to_ram(struct vm_fault *vmf)
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{
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struct nouveau_drm *drm = page_to_drm(vmf->page);
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struct nouveau_dmem *dmem = drm->dmem;
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struct nouveau_fence *fence;
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unsigned long src = 0, dst = 0;
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dma_addr_t dma_addr = 0;
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vm_fault_t ret;
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struct migrate_vma args = {
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.vma = vmf->vma,
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.start = vmf->address,
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.end = vmf->address + PAGE_SIZE,
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.src = &src,
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.dst = &dst,
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.pgmap_owner = drm->dev,
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.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE,
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};
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/*
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* FIXME what we really want is to find some heuristic to migrate more
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* than just one page on CPU fault. When such fault happens it is very
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* likely that more surrounding page will CPU fault too.
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*/
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if (migrate_vma_setup(&args) < 0)
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return VM_FAULT_SIGBUS;
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if (!args.cpages)
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return 0;
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ret = nouveau_dmem_fault_copy_one(drm, vmf, &args, &dma_addr);
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if (ret || dst == 0)
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goto done;
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nouveau_fence_new(dmem->migrate.chan, false, &fence);
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migrate_vma_pages(&args);
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nouveau_dmem_fence_done(&fence);
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dma_unmap_page(drm->dev->dev, dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
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done:
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migrate_vma_finalize(&args);
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return ret;
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}
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static const struct dev_pagemap_ops nouveau_dmem_pagemap_ops = {
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.page_free = nouveau_dmem_page_free,
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.migrate_to_ram = nouveau_dmem_migrate_to_ram,
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};
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static int
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nouveau_dmem_chunk_alloc(struct nouveau_drm *drm, struct page **ppage)
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{
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struct nouveau_dmem_chunk *chunk;
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struct resource *res;
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struct page *page;
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void *ptr;
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unsigned long i, pfn_first;
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int ret;
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chunk = kzalloc(sizeof(*chunk), GFP_KERNEL);
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if (chunk == NULL) {
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ret = -ENOMEM;
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goto out;
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}
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/* Allocate unused physical address space for device private pages. */
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res = request_free_mem_region(&iomem_resource, DMEM_CHUNK_SIZE,
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"nouveau_dmem");
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if (IS_ERR(res)) {
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ret = PTR_ERR(res);
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goto out_free;
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}
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chunk->drm = drm;
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chunk->pagemap.type = MEMORY_DEVICE_PRIVATE;
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chunk->pagemap.range.start = res->start;
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chunk->pagemap.range.end = res->end;
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chunk->pagemap.nr_range = 1;
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chunk->pagemap.ops = &nouveau_dmem_pagemap_ops;
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chunk->pagemap.owner = drm->dev;
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ret = nouveau_bo_new(&drm->client, DMEM_CHUNK_SIZE, 0,
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NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, NULL, NULL,
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&chunk->bo);
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if (ret)
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goto out_release;
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ret = nouveau_bo_pin(chunk->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
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if (ret)
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goto out_bo_free;
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ptr = memremap_pages(&chunk->pagemap, numa_node_id());
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if (IS_ERR(ptr)) {
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ret = PTR_ERR(ptr);
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goto out_bo_unpin;
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}
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mutex_lock(&drm->dmem->mutex);
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list_add(&chunk->list, &drm->dmem->chunks);
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mutex_unlock(&drm->dmem->mutex);
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pfn_first = chunk->pagemap.range.start >> PAGE_SHIFT;
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page = pfn_to_page(pfn_first);
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spin_lock(&drm->dmem->lock);
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for (i = 0; i < DMEM_CHUNK_NPAGES - 1; ++i, ++page) {
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page->zone_device_data = drm->dmem->free_pages;
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drm->dmem->free_pages = page;
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}
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*ppage = page;
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chunk->callocated++;
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spin_unlock(&drm->dmem->lock);
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NV_INFO(drm, "DMEM: registered %ldMB of device memory\n",
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DMEM_CHUNK_SIZE >> 20);
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return 0;
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out_bo_unpin:
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nouveau_bo_unpin(chunk->bo);
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out_bo_free:
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nouveau_bo_ref(NULL, &chunk->bo);
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out_release:
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release_mem_region(chunk->pagemap.range.start, range_len(&chunk->pagemap.range));
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out_free:
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kfree(chunk);
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out:
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return ret;
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}
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static struct page *
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nouveau_dmem_page_alloc_locked(struct nouveau_drm *drm)
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{
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struct nouveau_dmem_chunk *chunk;
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struct page *page = NULL;
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int ret;
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spin_lock(&drm->dmem->lock);
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if (drm->dmem->free_pages) {
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page = drm->dmem->free_pages;
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drm->dmem->free_pages = page->zone_device_data;
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chunk = nouveau_page_to_chunk(page);
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chunk->callocated++;
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spin_unlock(&drm->dmem->lock);
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} else {
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spin_unlock(&drm->dmem->lock);
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ret = nouveau_dmem_chunk_alloc(drm, &page);
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if (ret)
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return NULL;
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}
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get_page(page);
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lock_page(page);
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return page;
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}
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static void
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nouveau_dmem_page_free_locked(struct nouveau_drm *drm, struct page *page)
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{
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unlock_page(page);
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put_page(page);
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}
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void
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nouveau_dmem_resume(struct nouveau_drm *drm)
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{
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struct nouveau_dmem_chunk *chunk;
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int ret;
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if (drm->dmem == NULL)
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return;
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mutex_lock(&drm->dmem->mutex);
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list_for_each_entry(chunk, &drm->dmem->chunks, list) {
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ret = nouveau_bo_pin(chunk->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
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/* FIXME handle pin failure */
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WARN_ON(ret);
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}
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mutex_unlock(&drm->dmem->mutex);
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}
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void
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nouveau_dmem_suspend(struct nouveau_drm *drm)
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{
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struct nouveau_dmem_chunk *chunk;
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if (drm->dmem == NULL)
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return;
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mutex_lock(&drm->dmem->mutex);
|
|
list_for_each_entry(chunk, &drm->dmem->chunks, list)
|
|
nouveau_bo_unpin(chunk->bo);
|
|
mutex_unlock(&drm->dmem->mutex);
|
|
}
|
|
|
|
void
|
|
nouveau_dmem_fini(struct nouveau_drm *drm)
|
|
{
|
|
struct nouveau_dmem_chunk *chunk, *tmp;
|
|
|
|
if (drm->dmem == NULL)
|
|
return;
|
|
|
|
mutex_lock(&drm->dmem->mutex);
|
|
|
|
list_for_each_entry_safe(chunk, tmp, &drm->dmem->chunks, list) {
|
|
nouveau_bo_unpin(chunk->bo);
|
|
nouveau_bo_ref(NULL, &chunk->bo);
|
|
list_del(&chunk->list);
|
|
memunmap_pages(&chunk->pagemap);
|
|
release_mem_region(chunk->pagemap.range.start,
|
|
range_len(&chunk->pagemap.range));
|
|
kfree(chunk);
|
|
}
|
|
|
|
mutex_unlock(&drm->dmem->mutex);
|
|
}
|
|
|
|
static int
|
|
nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages,
|
|
enum nouveau_aper dst_aper, u64 dst_addr,
|
|
enum nouveau_aper src_aper, u64 src_addr)
|
|
{
|
|
struct nvif_push *push = drm->dmem->migrate.chan->chan.push;
|
|
u32 launch_dma = 0;
|
|
int ret;
|
|
|
|
ret = PUSH_WAIT(push, 13);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (src_aper != NOUVEAU_APER_VIRT) {
|
|
switch (src_aper) {
|
|
case NOUVEAU_APER_VRAM:
|
|
PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB));
|
|
break;
|
|
case NOUVEAU_APER_HOST:
|
|
PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM));
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, PHYSICAL);
|
|
}
|
|
|
|
if (dst_aper != NOUVEAU_APER_VIRT) {
|
|
switch (dst_aper) {
|
|
case NOUVEAU_APER_VRAM:
|
|
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));
|
|
break;
|
|
case NOUVEAU_APER_HOST:
|
|
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);
|
|
}
|
|
|
|
PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER,
|
|
NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(src_addr)),
|
|
|
|
OFFSET_IN_LOWER, lower_32_bits(src_addr),
|
|
|
|
OFFSET_OUT_UPPER,
|
|
NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)),
|
|
|
|
OFFSET_OUT_LOWER, lower_32_bits(dst_addr),
|
|
PITCH_IN, PAGE_SIZE,
|
|
PITCH_OUT, PAGE_SIZE,
|
|
LINE_LENGTH_IN, PAGE_SIZE,
|
|
LINE_COUNT, npages);
|
|
|
|
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING));
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length,
|
|
enum nouveau_aper dst_aper, u64 dst_addr)
|
|
{
|
|
struct nvif_push *push = drm->dmem->migrate.chan->chan.push;
|
|
u32 launch_dma = 0;
|
|
int ret;
|
|
|
|
ret = PUSH_WAIT(push, 12);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (dst_aper) {
|
|
case NOUVEAU_APER_VRAM:
|
|
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));
|
|
break;
|
|
case NOUVEAU_APER_HOST:
|
|
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
|
|
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);
|
|
|
|
PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
|
|
SET_REMAP_CONST_B, 0,
|
|
|
|
SET_REMAP_COMPONENTS,
|
|
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) |
|
|
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) |
|
|
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) |
|
|
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO));
|
|
|
|
PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
|
|
NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)),
|
|
|
|
OFFSET_OUT_LOWER, lower_32_bits(dst_addr));
|
|
|
|
PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
|
|
|
|
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) |
|
|
NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING));
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_dmem_migrate_init(struct nouveau_drm *drm)
|
|
{
|
|
switch (drm->ttm.copy.oclass) {
|
|
case PASCAL_DMA_COPY_A:
|
|
case PASCAL_DMA_COPY_B:
|
|
case VOLTA_DMA_COPY_A:
|
|
case TURING_DMA_COPY_A:
|
|
drm->dmem->migrate.copy_func = nvc0b5_migrate_copy;
|
|
drm->dmem->migrate.clear_func = nvc0b5_migrate_clear;
|
|
drm->dmem->migrate.chan = drm->ttm.chan;
|
|
return 0;
|
|
default:
|
|
break;
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
void
|
|
nouveau_dmem_init(struct nouveau_drm *drm)
|
|
{
|
|
int ret;
|
|
|
|
/* This only make sense on PASCAL or newer */
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_PASCAL)
|
|
return;
|
|
|
|
if (!(drm->dmem = kzalloc(sizeof(*drm->dmem), GFP_KERNEL)))
|
|
return;
|
|
|
|
drm->dmem->drm = drm;
|
|
mutex_init(&drm->dmem->mutex);
|
|
INIT_LIST_HEAD(&drm->dmem->chunks);
|
|
mutex_init(&drm->dmem->mutex);
|
|
spin_lock_init(&drm->dmem->lock);
|
|
|
|
/* Initialize migration dma helpers before registering memory */
|
|
ret = nouveau_dmem_migrate_init(drm);
|
|
if (ret) {
|
|
kfree(drm->dmem);
|
|
drm->dmem = NULL;
|
|
}
|
|
}
|
|
|
|
static unsigned long nouveau_dmem_migrate_copy_one(struct nouveau_drm *drm,
|
|
struct nouveau_svmm *svmm, unsigned long src,
|
|
dma_addr_t *dma_addr, u64 *pfn)
|
|
{
|
|
struct device *dev = drm->dev->dev;
|
|
struct page *dpage, *spage;
|
|
unsigned long paddr;
|
|
|
|
spage = migrate_pfn_to_page(src);
|
|
if (!(src & MIGRATE_PFN_MIGRATE))
|
|
goto out;
|
|
|
|
dpage = nouveau_dmem_page_alloc_locked(drm);
|
|
if (!dpage)
|
|
goto out;
|
|
|
|
paddr = nouveau_dmem_page_addr(dpage);
|
|
if (spage) {
|
|
*dma_addr = dma_map_page(dev, spage, 0, page_size(spage),
|
|
DMA_BIDIRECTIONAL);
|
|
if (dma_mapping_error(dev, *dma_addr))
|
|
goto out_free_page;
|
|
if (drm->dmem->migrate.copy_func(drm, 1,
|
|
NOUVEAU_APER_VRAM, paddr, NOUVEAU_APER_HOST, *dma_addr))
|
|
goto out_dma_unmap;
|
|
} else {
|
|
*dma_addr = DMA_MAPPING_ERROR;
|
|
if (drm->dmem->migrate.clear_func(drm, page_size(dpage),
|
|
NOUVEAU_APER_VRAM, paddr))
|
|
goto out_free_page;
|
|
}
|
|
|
|
dpage->zone_device_data = svmm;
|
|
*pfn = NVIF_VMM_PFNMAP_V0_V | NVIF_VMM_PFNMAP_V0_VRAM |
|
|
((paddr >> PAGE_SHIFT) << NVIF_VMM_PFNMAP_V0_ADDR_SHIFT);
|
|
if (src & MIGRATE_PFN_WRITE)
|
|
*pfn |= NVIF_VMM_PFNMAP_V0_W;
|
|
return migrate_pfn(page_to_pfn(dpage)) | MIGRATE_PFN_LOCKED;
|
|
|
|
out_dma_unmap:
|
|
dma_unmap_page(dev, *dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
|
|
out_free_page:
|
|
nouveau_dmem_page_free_locked(drm, dpage);
|
|
out:
|
|
*pfn = NVIF_VMM_PFNMAP_V0_NONE;
|
|
return 0;
|
|
}
|
|
|
|
static void nouveau_dmem_migrate_chunk(struct nouveau_drm *drm,
|
|
struct nouveau_svmm *svmm, struct migrate_vma *args,
|
|
dma_addr_t *dma_addrs, u64 *pfns)
|
|
{
|
|
struct nouveau_fence *fence;
|
|
unsigned long addr = args->start, nr_dma = 0, i;
|
|
|
|
for (i = 0; addr < args->end; i++) {
|
|
args->dst[i] = nouveau_dmem_migrate_copy_one(drm, svmm,
|
|
args->src[i], dma_addrs + nr_dma, pfns + i);
|
|
if (!dma_mapping_error(drm->dev->dev, dma_addrs[nr_dma]))
|
|
nr_dma++;
|
|
addr += PAGE_SIZE;
|
|
}
|
|
|
|
nouveau_fence_new(drm->dmem->migrate.chan, false, &fence);
|
|
migrate_vma_pages(args);
|
|
nouveau_dmem_fence_done(&fence);
|
|
nouveau_pfns_map(svmm, args->vma->vm_mm, args->start, pfns, i);
|
|
|
|
while (nr_dma--) {
|
|
dma_unmap_page(drm->dev->dev, dma_addrs[nr_dma], PAGE_SIZE,
|
|
DMA_BIDIRECTIONAL);
|
|
}
|
|
migrate_vma_finalize(args);
|
|
}
|
|
|
|
int
|
|
nouveau_dmem_migrate_vma(struct nouveau_drm *drm,
|
|
struct nouveau_svmm *svmm,
|
|
struct vm_area_struct *vma,
|
|
unsigned long start,
|
|
unsigned long end)
|
|
{
|
|
unsigned long npages = (end - start) >> PAGE_SHIFT;
|
|
unsigned long max = min(SG_MAX_SINGLE_ALLOC, npages);
|
|
dma_addr_t *dma_addrs;
|
|
struct migrate_vma args = {
|
|
.vma = vma,
|
|
.start = start,
|
|
.pgmap_owner = drm->dev,
|
|
.flags = MIGRATE_VMA_SELECT_SYSTEM,
|
|
};
|
|
unsigned long i;
|
|
u64 *pfns;
|
|
int ret = -ENOMEM;
|
|
|
|
if (drm->dmem == NULL)
|
|
return -ENODEV;
|
|
|
|
args.src = kcalloc(max, sizeof(*args.src), GFP_KERNEL);
|
|
if (!args.src)
|
|
goto out;
|
|
args.dst = kcalloc(max, sizeof(*args.dst), GFP_KERNEL);
|
|
if (!args.dst)
|
|
goto out_free_src;
|
|
|
|
dma_addrs = kmalloc_array(max, sizeof(*dma_addrs), GFP_KERNEL);
|
|
if (!dma_addrs)
|
|
goto out_free_dst;
|
|
|
|
pfns = nouveau_pfns_alloc(max);
|
|
if (!pfns)
|
|
goto out_free_dma;
|
|
|
|
for (i = 0; i < npages; i += max) {
|
|
args.end = start + (max << PAGE_SHIFT);
|
|
ret = migrate_vma_setup(&args);
|
|
if (ret)
|
|
goto out_free_pfns;
|
|
|
|
if (args.cpages)
|
|
nouveau_dmem_migrate_chunk(drm, svmm, &args, dma_addrs,
|
|
pfns);
|
|
args.start = args.end;
|
|
}
|
|
|
|
ret = 0;
|
|
out_free_pfns:
|
|
nouveau_pfns_free(pfns);
|
|
out_free_dma:
|
|
kfree(dma_addrs);
|
|
out_free_dst:
|
|
kfree(args.dst);
|
|
out_free_src:
|
|
kfree(args.src);
|
|
out:
|
|
return ret;
|
|
}
|