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085f1776fa
Add support for backplane link mode, which is, according to discussions with NXP earlier in the year, is a mode where the OS (Linux) is able to manage the PCS and Serdes itself. This commit prepares the ground work for allowing 1G fiber connections to be used with DPAA2 on the SolidRun CEX7 platforms. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
734 lines
20 KiB
C
734 lines
20 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2014-2016 Freescale Semiconductor Inc.
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* Copyright 2016-2020 NXP
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*/
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#ifndef __DPAA2_ETH_H
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#define __DPAA2_ETH_H
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#include <linux/dcbnl.h>
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/fsl/mc.h>
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#include <linux/net_tstamp.h>
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#include <net/devlink.h>
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#include <soc/fsl/dpaa2-io.h>
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#include <soc/fsl/dpaa2-fd.h>
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#include "dpni.h"
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#include "dpni-cmd.h"
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#include "dpaa2-eth-trace.h"
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#include "dpaa2-eth-debugfs.h"
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#include "dpaa2-mac.h"
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#define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
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#define DPAA2_ETH_STORE_SIZE 16
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/* Maximum number of scatter-gather entries in an ingress frame,
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* considering the maximum receive frame size is 64K
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*/
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#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
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/* Maximum acceptable MTU value. It is in direct relation with the hardware
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* enforced Max Frame Length (currently 10k).
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*/
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#define DPAA2_ETH_MFL (10 * 1024)
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#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
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/* Convert L3 MTU to L2 MFL */
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#define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
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/* Set the taildrop threshold (in bytes) to allow the enqueue of a large
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* enough number of jumbo frames in the Rx queues (length of the current
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* frame is not taken into account when making the taildrop decision)
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*/
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#define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
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/* Maximum burst size value for Tx shaping */
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#define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
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/* Maximum number of Tx confirmation frames to be processed
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* in a single NAPI call
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*/
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#define DPAA2_ETH_TXCONF_PER_NAPI 256
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/* Buffer qouta per channel. We want to keep in check number of ingress frames
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* in flight: for small sized frames, congestion group taildrop may kick in
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* first; for large sizes, Rx FQ taildrop threshold will ensure only a
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* reasonable number of frames will be pending at any given time.
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* Ingress frame drop due to buffer pool depletion should be a corner case only
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*/
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#define DPAA2_ETH_NUM_BUFS 1280
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#define DPAA2_ETH_REFILL_THRESH \
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(DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
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/* Congestion group taildrop threshold: number of frames allowed to accumulate
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* at any moment in a group of Rx queues belonging to the same traffic class.
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* Choose value such that we don't risk depleting the buffer pool before the
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* taildrop kicks in
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*/
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#define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
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(1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
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/* Congestion group notification threshold: when this many frames accumulate
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* on the Rx queues belonging to the same TC, the MAC is instructed to send
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* PFC frames for that TC.
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* When number of pending frames drops below exit threshold transmission of
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* PFC frames is stopped.
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*/
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#define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
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(DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
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#define DPAA2_ETH_CN_THRESH_EXIT(priv) \
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(DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
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/* Maximum number of buffers that can be acquired/released through a single
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* QBMan command
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*/
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#define DPAA2_ETH_BUFS_PER_CMD 7
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/* Hardware requires alignment for ingress/egress buffer addresses */
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#define DPAA2_ETH_TX_BUF_ALIGN 64
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#define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
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#define DPAA2_ETH_RX_BUF_TAILROOM \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
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#define DPAA2_ETH_RX_BUF_SIZE \
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(DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
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/* Hardware annotation area in RX/TX buffers */
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#define DPAA2_ETH_RX_HWA_SIZE 64
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#define DPAA2_ETH_TX_HWA_SIZE 128
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/* PTP nominal frequency 1GHz */
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#define DPAA2_PTP_CLK_PERIOD_NS 1
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/* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
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* to 256B. For newer revisions, the requirement is only for 64B alignment
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*/
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#define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
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#define DPAA2_ETH_RX_BUF_ALIGN 64
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/* We are accommodating a skb backpointer and some S/G info
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* in the frame's software annotation. The hardware
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* options are either 0 or 64, so we choose the latter.
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*/
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#define DPAA2_ETH_SWA_SIZE 64
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/* We store different information in the software annotation area of a Tx frame
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* based on what type of frame it is
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*/
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enum dpaa2_eth_swa_type {
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DPAA2_ETH_SWA_SINGLE,
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DPAA2_ETH_SWA_SG,
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DPAA2_ETH_SWA_XDP,
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};
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/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
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struct dpaa2_eth_swa {
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enum dpaa2_eth_swa_type type;
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union {
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struct {
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struct sk_buff *skb;
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int sgt_size;
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} single;
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struct {
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struct sk_buff *skb;
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struct scatterlist *scl;
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int num_sg;
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int sgt_size;
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} sg;
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struct {
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int dma_size;
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struct xdp_frame *xdpf;
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} xdp;
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};
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};
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/* Annotation valid bits in FD FRC */
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#define DPAA2_FD_FRC_FASV 0x8000
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#define DPAA2_FD_FRC_FAEADV 0x4000
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#define DPAA2_FD_FRC_FAPRV 0x2000
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#define DPAA2_FD_FRC_FAIADV 0x1000
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#define DPAA2_FD_FRC_FASWOV 0x0800
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#define DPAA2_FD_FRC_FAICFDV 0x0400
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/* Error bits in FD CTRL */
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#define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
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#define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
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FD_CTRL_SBE | \
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FD_CTRL_FSE | \
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FD_CTRL_FAERR)
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/* Annotation bits in FD CTRL */
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#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
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/* Frame annotation status */
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struct dpaa2_fas {
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u8 reserved;
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u8 ppid;
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__le16 ifpid;
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__le32 status;
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};
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/* Frame annotation status word is located in the first 8 bytes
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* of the buffer's hardware annoatation area
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*/
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#define DPAA2_FAS_OFFSET 0
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#define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
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/* Timestamp is located in the next 8 bytes of the buffer's
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* hardware annotation area
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*/
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#define DPAA2_TS_OFFSET 0x8
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/* Frame annotation parse results */
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struct dpaa2_fapr {
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/* 64-bit word 1 */
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__le32 faf_lo;
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__le16 faf_ext;
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__le16 nxt_hdr;
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/* 64-bit word 2 */
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__le64 faf_hi;
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/* 64-bit word 3 */
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u8 last_ethertype_offset;
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u8 vlan_tci_offset_n;
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u8 vlan_tci_offset_1;
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u8 llc_snap_offset;
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u8 eth_offset;
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u8 ip1_pid_offset;
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u8 shim_offset_2;
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u8 shim_offset_1;
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/* 64-bit word 4 */
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u8 l5_offset;
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u8 l4_offset;
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u8 gre_offset;
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u8 l3_offset_n;
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u8 l3_offset_1;
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u8 mpls_offset_n;
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u8 mpls_offset_1;
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u8 pppoe_offset;
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/* 64-bit word 5 */
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__le16 running_sum;
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__le16 gross_running_sum;
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u8 ipv6_frag_offset;
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u8 nxt_hdr_offset;
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u8 routing_hdr_offset_2;
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u8 routing_hdr_offset_1;
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/* 64-bit word 6 */
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u8 reserved[5]; /* Soft-parsing context */
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u8 ip_proto_offset_n;
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u8 nxt_hdr_frag_offset;
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u8 parse_error_code;
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};
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#define DPAA2_FAPR_OFFSET 0x10
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#define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
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/* Frame annotation egress action descriptor */
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#define DPAA2_FAEAD_OFFSET 0x58
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struct dpaa2_faead {
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__le32 conf_fqid;
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__le32 ctrl;
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};
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#define DPAA2_FAEAD_A2V 0x20000000
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#define DPAA2_FAEAD_A4V 0x08000000
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#define DPAA2_FAEAD_UPDV 0x00001000
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#define DPAA2_FAEAD_EBDDV 0x00002000
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#define DPAA2_FAEAD_UPD 0x00000010
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struct ptp_tstamp {
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u16 sec_msb;
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u32 sec_lsb;
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u32 nsec;
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};
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static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
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{
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u64 sec, nsec;
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sec = ns;
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nsec = do_div(sec, 1000000000);
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tstamp->sec_lsb = sec & 0xFFFFFFFF;
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tstamp->sec_msb = (sec >> 32) & 0xFFFF;
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tstamp->nsec = nsec;
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}
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/* Accessors for the hardware annotation fields that we use */
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static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
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{
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return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
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}
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static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
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{
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return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
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}
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static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
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{
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return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
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}
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static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
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{
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return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
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}
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static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
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{
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return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
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}
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/* Error and status bits in the frame annotation status word */
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/* Debug frame, otherwise supposed to be discarded */
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#define DPAA2_FAS_DISC 0x80000000
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/* MACSEC frame */
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#define DPAA2_FAS_MS 0x40000000
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#define DPAA2_FAS_PTP 0x08000000
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/* Ethernet multicast frame */
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#define DPAA2_FAS_MC 0x04000000
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/* Ethernet broadcast frame */
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#define DPAA2_FAS_BC 0x02000000
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#define DPAA2_FAS_KSE 0x00040000
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#define DPAA2_FAS_EOFHE 0x00020000
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#define DPAA2_FAS_MNLE 0x00010000
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#define DPAA2_FAS_TIDE 0x00008000
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#define DPAA2_FAS_PIEE 0x00004000
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/* Frame length error */
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#define DPAA2_FAS_FLE 0x00002000
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/* Frame physical error */
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#define DPAA2_FAS_FPE 0x00001000
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#define DPAA2_FAS_PTE 0x00000080
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#define DPAA2_FAS_ISP 0x00000040
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#define DPAA2_FAS_PHE 0x00000020
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#define DPAA2_FAS_BLE 0x00000010
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/* L3 csum validation performed */
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#define DPAA2_FAS_L3CV 0x00000008
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/* L3 csum error */
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#define DPAA2_FAS_L3CE 0x00000004
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/* L4 csum validation performed */
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#define DPAA2_FAS_L4CV 0x00000002
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/* L4 csum error */
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#define DPAA2_FAS_L4CE 0x00000001
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/* Possible errors on the ingress path */
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#define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
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DPAA2_FAS_EOFHE | \
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DPAA2_FAS_MNLE | \
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DPAA2_FAS_TIDE | \
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DPAA2_FAS_PIEE | \
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DPAA2_FAS_FLE | \
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DPAA2_FAS_FPE | \
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DPAA2_FAS_PTE | \
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DPAA2_FAS_ISP | \
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DPAA2_FAS_PHE | \
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DPAA2_FAS_BLE | \
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DPAA2_FAS_L3CE | \
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DPAA2_FAS_L4CE)
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/* Time in milliseconds between link state updates */
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#define DPAA2_ETH_LINK_STATE_REFRESH 1000
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/* Number of times to retry a frame enqueue before giving up.
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* Value determined empirically, in order to minimize the number
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* of frames dropped on Tx
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*/
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#define DPAA2_ETH_ENQUEUE_RETRIES 10
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/* Number of times to retry DPIO portal operations while waiting
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* for portal to finish executing current command and become
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* available. We want to avoid being stuck in a while loop in case
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* hardware becomes unresponsive, but not give up too easily if
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* the portal really is busy for valid reasons
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*/
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#define DPAA2_ETH_SWP_BUSY_RETRIES 1000
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/* Driver statistics, other than those in struct rtnl_link_stats64.
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* These are usually collected per-CPU and aggregated by ethtool.
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*/
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struct dpaa2_eth_drv_stats {
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__u64 tx_conf_frames;
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__u64 tx_conf_bytes;
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__u64 tx_sg_frames;
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__u64 tx_sg_bytes;
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__u64 rx_sg_frames;
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__u64 rx_sg_bytes;
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/* Linear skbs sent as a S/G FD due to insufficient headroom */
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__u64 tx_converted_sg_frames;
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__u64 tx_converted_sg_bytes;
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/* Enqueues retried due to portal busy */
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__u64 tx_portal_busy;
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};
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/* Per-FQ statistics */
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struct dpaa2_eth_fq_stats {
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/* Number of frames received on this queue */
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__u64 frames;
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};
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/* Per-channel statistics */
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struct dpaa2_eth_ch_stats {
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/* Volatile dequeues retried due to portal busy */
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__u64 dequeue_portal_busy;
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/* Pull errors */
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__u64 pull_err;
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/* Number of CDANs; useful to estimate avg NAPI len */
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__u64 cdan;
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/* XDP counters */
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__u64 xdp_drop;
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__u64 xdp_tx;
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__u64 xdp_tx_err;
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__u64 xdp_redirect;
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/* Must be last, does not show up in ethtool stats */
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__u64 frames;
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};
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/* Maximum number of queues associated with a DPNI */
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#define DPAA2_ETH_MAX_TCS 8
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#define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
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#define DPAA2_ETH_MAX_RX_QUEUES \
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(DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
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#define DPAA2_ETH_MAX_TX_QUEUES 16
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#define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
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#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
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DPAA2_ETH_MAX_TX_QUEUES + \
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DPAA2_ETH_MAX_RX_ERR_QUEUES)
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#define DPAA2_ETH_MAX_NETDEV_QUEUES \
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(DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
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#define DPAA2_ETH_MAX_DPCONS 16
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enum dpaa2_eth_fq_type {
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DPAA2_RX_FQ = 0,
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DPAA2_TX_CONF_FQ,
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DPAA2_RX_ERR_FQ
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};
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struct dpaa2_eth_priv;
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struct dpaa2_eth_xdp_fds {
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struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
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ssize_t num;
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};
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struct dpaa2_eth_fq {
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u32 fqid;
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u32 tx_qdbin;
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u32 tx_fqid[DPAA2_ETH_MAX_TCS];
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u16 flowid;
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u8 tc;
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int target_cpu;
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u32 dq_frames;
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u32 dq_bytes;
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struct dpaa2_eth_channel *channel;
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enum dpaa2_eth_fq_type type;
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void (*consume)(struct dpaa2_eth_priv *priv,
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struct dpaa2_eth_channel *ch,
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const struct dpaa2_fd *fd,
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struct dpaa2_eth_fq *fq);
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struct dpaa2_eth_fq_stats stats;
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struct dpaa2_eth_xdp_fds xdp_redirect_fds;
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struct dpaa2_eth_xdp_fds xdp_tx_fds;
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};
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struct dpaa2_eth_ch_xdp {
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struct bpf_prog *prog;
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u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD];
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int drop_cnt;
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unsigned int res;
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};
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struct dpaa2_eth_channel {
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struct dpaa2_io_notification_ctx nctx;
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struct fsl_mc_device *dpcon;
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int dpcon_id;
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int ch_id;
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struct napi_struct napi;
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struct dpaa2_io *dpio;
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struct dpaa2_io_store *store;
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struct dpaa2_eth_priv *priv;
|
|
int buf_count;
|
|
struct dpaa2_eth_ch_stats stats;
|
|
struct dpaa2_eth_ch_xdp xdp;
|
|
struct xdp_rxq_info xdp_rxq;
|
|
struct list_head *rx_list;
|
|
};
|
|
|
|
struct dpaa2_eth_dist_fields {
|
|
u64 rxnfc_field;
|
|
enum net_prot cls_prot;
|
|
int cls_field;
|
|
int size;
|
|
u64 id;
|
|
};
|
|
|
|
struct dpaa2_eth_cls_rule {
|
|
struct ethtool_rx_flow_spec fs;
|
|
u8 in_use;
|
|
};
|
|
|
|
#define DPAA2_ETH_SGT_CACHE_SIZE 256
|
|
struct dpaa2_eth_sgt_cache {
|
|
void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
|
|
u16 count;
|
|
};
|
|
|
|
struct dpaa2_eth_trap_item {
|
|
void *trap_ctx;
|
|
};
|
|
|
|
struct dpaa2_eth_trap_data {
|
|
struct dpaa2_eth_trap_item *trap_items_arr;
|
|
struct dpaa2_eth_priv *priv;
|
|
};
|
|
|
|
/* Driver private data */
|
|
struct dpaa2_eth_priv {
|
|
struct net_device *net_dev;
|
|
|
|
u8 num_fqs;
|
|
struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
|
|
int (*enqueue)(struct dpaa2_eth_priv *priv,
|
|
struct dpaa2_eth_fq *fq,
|
|
struct dpaa2_fd *fd, u8 prio,
|
|
u32 num_frames,
|
|
int *frames_enqueued);
|
|
|
|
u8 num_channels;
|
|
struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
|
|
struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
|
|
|
|
struct dpni_attr dpni_attrs;
|
|
u16 dpni_ver_major;
|
|
u16 dpni_ver_minor;
|
|
u16 tx_data_offset;
|
|
|
|
struct fsl_mc_device *dpbp_dev;
|
|
u16 rx_buf_size;
|
|
u16 bpid;
|
|
struct iommu_domain *iommu_domain;
|
|
|
|
enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */
|
|
bool rx_tstamp; /* Rx timestamping enabled */
|
|
|
|
u16 tx_qdid;
|
|
struct fsl_mc_io *mc_io;
|
|
/* Cores which have an affine DPIO/DPCON.
|
|
* This is the cpu set on which Rx and Tx conf frames are processed
|
|
*/
|
|
struct cpumask dpio_cpumask;
|
|
|
|
/* Standard statistics */
|
|
struct rtnl_link_stats64 __percpu *percpu_stats;
|
|
/* Extra stats, in addition to the ones known by the kernel */
|
|
struct dpaa2_eth_drv_stats __percpu *percpu_extras;
|
|
|
|
u16 mc_token;
|
|
u8 rx_fqtd_enabled;
|
|
u8 rx_cgtd_enabled;
|
|
|
|
struct dpni_link_state link_state;
|
|
bool do_link_poll;
|
|
struct task_struct *poll_thread;
|
|
|
|
/* enabled ethtool hashing bits */
|
|
u64 rx_hash_fields;
|
|
u64 rx_cls_fields;
|
|
struct dpaa2_eth_cls_rule *cls_rules;
|
|
u8 rx_cls_enabled;
|
|
u8 vlan_cls_enabled;
|
|
u8 pfc_enabled;
|
|
#ifdef CONFIG_FSL_DPAA2_ETH_DCB
|
|
u8 dcbx_mode;
|
|
struct ieee_pfc pfc;
|
|
#endif
|
|
struct bpf_prog *xdp_prog;
|
|
#ifdef CONFIG_DEBUG_FS
|
|
struct dpaa2_debugfs dbg;
|
|
#endif
|
|
|
|
struct dpaa2_mac *mac;
|
|
struct workqueue_struct *dpaa2_ptp_wq;
|
|
struct work_struct tx_onestep_tstamp;
|
|
struct sk_buff_head tx_skbs;
|
|
/* The one-step timestamping configuration on hardware
|
|
* registers could only be done when no one-step
|
|
* timestamping frames are in flight. So we use a mutex
|
|
* lock here to make sure the lock is released by last
|
|
* one-step timestamping packet through TX confirmation
|
|
* queue before transmit current packet.
|
|
*/
|
|
struct mutex onestep_tstamp_lock;
|
|
struct devlink *devlink;
|
|
struct dpaa2_eth_trap_data *trap_data;
|
|
struct devlink_port devlink_port;
|
|
};
|
|
|
|
struct dpaa2_eth_devlink_priv {
|
|
struct dpaa2_eth_priv *dpaa2_priv;
|
|
};
|
|
|
|
#define TX_TSTAMP 0x1
|
|
#define TX_TSTAMP_ONESTEP_SYNC 0x2
|
|
|
|
#define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
|
|
| RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
|
|
| RXH_L4_B_2_3)
|
|
|
|
/* default Rx hash options, set during probing */
|
|
#define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
|
|
RXH_L4_B_0_1 | RXH_L4_B_2_3)
|
|
|
|
#define dpaa2_eth_hash_enabled(priv) \
|
|
((priv)->dpni_attrs.num_queues > 1)
|
|
|
|
/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
|
|
#define DPAA2_CLASSIFIER_DMA_SIZE 256
|
|
|
|
extern const struct ethtool_ops dpaa2_ethtool_ops;
|
|
extern int dpaa2_phc_index;
|
|
extern struct ptp_qoriq *dpaa2_ptp;
|
|
|
|
static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
|
|
u16 ver_major, u16 ver_minor)
|
|
{
|
|
if (priv->dpni_ver_major == ver_major)
|
|
return priv->dpni_ver_minor - ver_minor;
|
|
return priv->dpni_ver_major - ver_major;
|
|
}
|
|
|
|
/* Minimum firmware version that supports a more flexible API
|
|
* for configuring the Rx flow hash key
|
|
*/
|
|
#define DPNI_RX_DIST_KEY_VER_MAJOR 7
|
|
#define DPNI_RX_DIST_KEY_VER_MINOR 5
|
|
|
|
#define dpaa2_eth_has_legacy_dist(priv) \
|
|
(dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
|
|
DPNI_RX_DIST_KEY_VER_MINOR) < 0)
|
|
|
|
#define dpaa2_eth_fs_enabled(priv) \
|
|
(!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
|
|
|
|
#define dpaa2_eth_fs_mask_enabled(priv) \
|
|
((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
|
|
|
|
#define dpaa2_eth_fs_count(priv) \
|
|
((priv)->dpni_attrs.fs_entries)
|
|
|
|
#define dpaa2_eth_tc_count(priv) \
|
|
((priv)->dpni_attrs.num_tcs)
|
|
|
|
/* We have exactly one {Rx, Tx conf} queue per channel */
|
|
#define dpaa2_eth_queue_count(priv) \
|
|
((priv)->num_channels)
|
|
|
|
enum dpaa2_eth_rx_dist {
|
|
DPAA2_ETH_RX_DIST_HASH,
|
|
DPAA2_ETH_RX_DIST_CLS
|
|
};
|
|
|
|
/* Unique IDs for the supported Rx classification header fields */
|
|
#define DPAA2_ETH_DIST_ETHDST BIT(0)
|
|
#define DPAA2_ETH_DIST_ETHSRC BIT(1)
|
|
#define DPAA2_ETH_DIST_ETHTYPE BIT(2)
|
|
#define DPAA2_ETH_DIST_VLAN BIT(3)
|
|
#define DPAA2_ETH_DIST_IPSRC BIT(4)
|
|
#define DPAA2_ETH_DIST_IPDST BIT(5)
|
|
#define DPAA2_ETH_DIST_IPPROTO BIT(6)
|
|
#define DPAA2_ETH_DIST_L4SRC BIT(7)
|
|
#define DPAA2_ETH_DIST_L4DST BIT(8)
|
|
#define DPAA2_ETH_DIST_ALL (~0ULL)
|
|
|
|
#define DPNI_PAUSE_VER_MAJOR 7
|
|
#define DPNI_PAUSE_VER_MINOR 13
|
|
#define dpaa2_eth_has_pause_support(priv) \
|
|
(dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
|
|
DPNI_PAUSE_VER_MINOR) >= 0)
|
|
|
|
static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
|
|
{
|
|
return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
|
|
!!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
|
|
}
|
|
|
|
static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
|
|
{
|
|
return !!(link_options & DPNI_LINK_OPT_PAUSE);
|
|
}
|
|
|
|
static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
|
|
{
|
|
unsigned int headroom = DPAA2_ETH_SWA_SIZE;
|
|
|
|
/* If we don't have an skb (e.g. XDP buffer), we only need space for
|
|
* the software annotation area
|
|
*/
|
|
if (!skb)
|
|
return headroom;
|
|
|
|
/* For non-linear skbs we have no headroom requirement, as we build a
|
|
* SG frame with a newly allocated SGT buffer
|
|
*/
|
|
if (skb_is_nonlinear(skb))
|
|
return 0;
|
|
|
|
/* If we have Tx timestamping, need 128B hardware annotation */
|
|
if (skb->cb[0])
|
|
headroom += DPAA2_ETH_TX_HWA_SIZE;
|
|
|
|
return headroom;
|
|
}
|
|
|
|
/* Extra headroom space requested to hardware, in order to make sure there's
|
|
* no realloc'ing in forwarding scenarios
|
|
*/
|
|
static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
|
|
{
|
|
return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
|
|
}
|
|
|
|
static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
|
|
{
|
|
if (priv->mac &&
|
|
(priv->mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
|
|
priv->mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
|
|
{
|
|
return priv->mac ? true : false;
|
|
}
|
|
|
|
int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
|
|
int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
|
|
int dpaa2_eth_cls_key_size(u64 key);
|
|
int dpaa2_eth_cls_fld_off(int prot, int field);
|
|
void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
|
|
|
|
void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
|
|
bool tx_pause, bool pfc);
|
|
|
|
extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
|
|
|
|
int dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
|
|
void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
|
|
|
|
int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
|
|
void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
|
|
|
|
int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
|
|
void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
|
|
|
|
struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
|
|
struct dpaa2_fapr *fapr);
|
|
#endif /* __DPAA2_H */
|