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cbb796ccd8
dmaengine drivers should always use sg_dma_address instead of sg_phys to get the addresses for the transfer from a sg element. To quote Russel King: sg_phys(sg) of course has nothing to do with DMA addresses. It's the physical address _to the CPU_ of the memory associated with the scatterlist entry. That may, or may not have the same value for the DMA engine, particularly if IOMMUs are involved. And if these drivers are used on ARM, they must be fixed, sooner rather than later. There's patches in the works which will mean we will end up with IOMMU support in the DMA mapping later, which means everything I've said above will become reality. The patch has been generated using the following coccinelle patch: <smpl> @@ struct scatterlist *sg; @@ -sg_phys(sg) +sg_dma_address(sg) </smpl> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
314 lines
6.3 KiB
C
314 lines
6.3 KiB
C
/*
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* driver/dma/coh901318_lli.c
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* Support functions for handling lli for dma
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#include <linux/spinlock.h>
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#include <linux/memory.h>
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#include <linux/gfp.h>
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#include <linux/dmapool.h>
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#include <mach/coh901318.h>
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#include "coh901318_lli.h"
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#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
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#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
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#else
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#define DEBUGFS_POOL_COUNTER_RESET(pool)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add)
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#endif
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static struct coh901318_lli *
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coh901318_lli_next(struct coh901318_lli *data)
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{
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if (data == NULL || data->link_addr == 0)
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return NULL;
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return (struct coh901318_lli *) data->virt_link_addr;
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}
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int coh901318_pool_create(struct coh901318_pool *pool,
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struct device *dev,
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size_t size, size_t align)
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{
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spin_lock_init(&pool->lock);
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pool->dev = dev;
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pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
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DEBUGFS_POOL_COUNTER_RESET(pool);
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return 0;
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}
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int coh901318_pool_destroy(struct coh901318_pool *pool)
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{
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dma_pool_destroy(pool->dmapool);
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return 0;
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}
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struct coh901318_lli *
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coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
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{
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int i;
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struct coh901318_lli *head;
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struct coh901318_lli *lli;
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struct coh901318_lli *lli_prev;
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dma_addr_t phy;
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if (len == 0)
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goto err;
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spin_lock(&pool->lock);
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head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (head == NULL)
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goto err;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli = head;
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lli->phy_this = phy;
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lli->link_addr = 0x00000000;
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lli->virt_link_addr = 0x00000000U;
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for (i = 1; i < len; i++) {
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lli_prev = lli;
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lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (lli == NULL)
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goto err_clean_up;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli->phy_this = phy;
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lli->link_addr = 0x00000000;
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lli->virt_link_addr = 0x00000000U;
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lli_prev->link_addr = phy;
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lli_prev->virt_link_addr = lli;
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}
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spin_unlock(&pool->lock);
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return head;
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err:
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spin_unlock(&pool->lock);
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return NULL;
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err_clean_up:
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lli_prev->link_addr = 0x00000000U;
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spin_unlock(&pool->lock);
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coh901318_lli_free(pool, &head);
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return NULL;
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}
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void coh901318_lli_free(struct coh901318_pool *pool,
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struct coh901318_lli **lli)
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{
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struct coh901318_lli *l;
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struct coh901318_lli *next;
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if (lli == NULL)
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return;
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l = *lli;
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if (l == NULL)
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return;
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spin_lock(&pool->lock);
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while (l->link_addr) {
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next = l->virt_link_addr;
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dma_pool_free(pool->dmapool, l, l->phy_this);
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DEBUGFS_POOL_COUNTER_ADD(pool, -1);
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l = next;
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}
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dma_pool_free(pool->dmapool, l, l->phy_this);
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DEBUGFS_POOL_COUNTER_ADD(pool, -1);
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spin_unlock(&pool->lock);
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*lli = NULL;
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}
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int
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coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t source, unsigned int size,
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dma_addr_t destination, u32 ctrl_chained,
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u32 ctrl_eom)
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{
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int s = size;
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dma_addr_t src = source;
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dma_addr_t dst = destination;
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lli->src_addr = src;
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lli->dst_addr = dst;
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while (lli->link_addr) {
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lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
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lli->src_addr = src;
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lli->dst_addr = dst;
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s -= MAX_DMA_PACKET_SIZE;
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lli = coh901318_lli_next(lli);
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src += MAX_DMA_PACKET_SIZE;
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dst += MAX_DMA_PACKET_SIZE;
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}
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lli->control = ctrl_eom | s;
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lli->src_addr = src;
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lli->dst_addr = dst;
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return 0;
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}
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int
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coh901318_lli_fill_single(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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dma_addr_t buf, unsigned int size,
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dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
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enum dma_transfer_direction dir)
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{
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int s = size;
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dma_addr_t src;
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dma_addr_t dst;
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if (dir == DMA_MEM_TO_DEV) {
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src = buf;
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dst = dev_addr;
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} else if (dir == DMA_DEV_TO_MEM) {
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src = dev_addr;
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dst = buf;
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} else {
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return -EINVAL;
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}
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while (lli->link_addr) {
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size_t block_size = MAX_DMA_PACKET_SIZE;
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lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
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/* If we are on the next-to-final block and there will
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* be less than half a DMA packet left for the last
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* block, then we want to make this block a little
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* smaller to balance the sizes. This is meant to
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* avoid too small transfers if the buffer size is
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* (MAX_DMA_PACKET_SIZE*N + 1) */
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if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
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block_size = MAX_DMA_PACKET_SIZE/2;
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s -= block_size;
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lli->src_addr = src;
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lli->dst_addr = dst;
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lli = coh901318_lli_next(lli);
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if (dir == DMA_MEM_TO_DEV)
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src += block_size;
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else if (dir == DMA_DEV_TO_MEM)
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dst += block_size;
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}
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lli->control = ctrl_eom | s;
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lli->src_addr = src;
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lli->dst_addr = dst;
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return 0;
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}
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int
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coh901318_lli_fill_sg(struct coh901318_pool *pool,
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struct coh901318_lli *lli,
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struct scatterlist *sgl, unsigned int nents,
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dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
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u32 ctrl_last,
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enum dma_transfer_direction dir, u32 ctrl_irq_mask)
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{
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int i;
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struct scatterlist *sg;
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u32 ctrl_sg;
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dma_addr_t src = 0;
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dma_addr_t dst = 0;
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u32 bytes_to_transfer;
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u32 elem_size;
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if (lli == NULL)
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goto err;
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spin_lock(&pool->lock);
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if (dir == DMA_MEM_TO_DEV)
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dst = dev_addr;
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else if (dir == DMA_DEV_TO_MEM)
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src = dev_addr;
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else
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goto err;
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for_each_sg(sgl, sg, nents, i) {
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if (sg_is_chain(sg)) {
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/* sg continues to the next sg-element don't
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* send ctrl_finish until the last
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* sg-element in the chain
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*/
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ctrl_sg = ctrl_chained;
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} else if (i == nents - 1)
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ctrl_sg = ctrl_last;
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else
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ctrl_sg = ctrl ? ctrl : ctrl_last;
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if (dir == DMA_MEM_TO_DEV)
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/* increment source address */
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src = sg_dma_address(sg);
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else
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/* increment destination address */
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dst = sg_dma_address(sg);
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bytes_to_transfer = sg_dma_len(sg);
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while (bytes_to_transfer) {
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u32 val;
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if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
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elem_size = MAX_DMA_PACKET_SIZE;
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val = ctrl_chained;
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} else {
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elem_size = bytes_to_transfer;
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val = ctrl_sg;
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}
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lli->control = val | elem_size;
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lli->src_addr = src;
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lli->dst_addr = dst;
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if (dir == DMA_DEV_TO_MEM)
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dst += elem_size;
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else
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src += elem_size;
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BUG_ON(lli->link_addr & 3);
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bytes_to_transfer -= elem_size;
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lli = coh901318_lli_next(lli);
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}
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}
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spin_unlock(&pool->lock);
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return 0;
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err:
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spin_unlock(&pool->lock);
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return -EINVAL;
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}
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