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b1f778a223
Huang Shijie reports that, when profiling a guest from the host with a number of events that exceeds the number of available counters, the reported counts are wildly inaccurate. Without the counter oversubscription, the reported counts are correct. Their investigation indicates that upon counter rotation (which takes place on the back of a timer interrupt), we fail to re-apply the guest EL0 enabling, leading to the counting of host events instead of guest events. In order to solve this, add yet another hook between the host PMU driver and KVM, re-applying the guest EL0 configuration if the right conditions apply (the host is VHE, we are in interrupt context, and we interrupted a running vcpu). This triggers a new vcpu request which will apply the correct configuration on guest reentry. With this, we have the correct counts, even when the counters are oversubscribed. Reported-by: Huang Shijie <shijie@os.amperecomputing.com> Suggested-by: Oliver Upton <oliver.upton@linux.dev> Tested_by: Huang Shijie <shijie@os.amperecomputing.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20230809013953.7692-1-shijie@os.amperecomputing.com Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20230820090108.177817-1-maz@kernel.org
180 lines
5.5 KiB
C
180 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Shannon Zhao <shannon.zhao@linaro.org>
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*/
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#ifndef __ASM_ARM_KVM_PMU_H
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#define __ASM_ARM_KVM_PMU_H
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#include <linux/perf_event.h>
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#include <linux/perf/arm_pmuv3.h>
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#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
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#ifdef CONFIG_HW_PERF_EVENTS
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struct kvm_pmc {
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u8 idx; /* index into the pmu->pmc array */
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struct perf_event *perf_event;
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};
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struct kvm_pmu_events {
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u32 events_host;
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u32 events_guest;
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};
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struct kvm_pmu {
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struct irq_work overflow_work;
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struct kvm_pmu_events events;
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struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
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int irq_num;
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bool created;
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bool irq_level;
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};
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struct arm_pmu_entry {
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struct list_head entry;
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struct arm_pmu *arm_pmu;
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};
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DECLARE_STATIC_KEY_FALSE(kvm_arm_pmu_available);
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static __always_inline bool kvm_arm_support_pmu_v3(void)
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{
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return static_branch_likely(&kvm_arm_pmu_available);
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}
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#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
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u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);
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void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
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void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
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bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
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void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
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void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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u64 select_idx);
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int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
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struct kvm_pmu_events *kvm_get_pmu_events(void);
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void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
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void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
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void kvm_vcpu_pmu_resync_el0(void);
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#define kvm_vcpu_has_pmu(vcpu) \
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(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
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/*
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* Updates the vcpu's view of the pmu events for this cpu.
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* Must be called before every vcpu run after disabling interrupts, to ensure
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* that an interrupt cannot fire and update the structure.
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*/
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#define kvm_pmu_update_vcpu_events(vcpu) \
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do { \
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if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \
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vcpu->arch.pmu.events = *kvm_get_pmu_events(); \
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} while (0)
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/*
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* Evaluates as true when emulating PMUv3p5, and false otherwise.
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*/
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#define kvm_pmu_is_3p5(vcpu) ({ \
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u64 val = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); \
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u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); \
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\
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pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5; \
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})
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u8 kvm_arm_pmu_get_pmuver_limit(void);
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#else
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struct kvm_pmu {
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};
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static inline bool kvm_arm_support_pmu_v3(void)
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{
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return false;
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}
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#define kvm_arm_pmu_irq_initialized(v) (false)
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static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx)
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{
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return 0;
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}
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static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx, u64 val) {}
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static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
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static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
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{
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return false;
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}
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static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
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u64 data, u64 select_idx) {}
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static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
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{
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return 0;
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}
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#define kvm_vcpu_has_pmu(vcpu) ({ false; })
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#define kvm_pmu_is_3p5(vcpu) ({ false; })
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static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
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static inline u8 kvm_arm_pmu_get_pmuver_limit(void)
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{
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return 0;
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}
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static inline void kvm_vcpu_pmu_resync_el0(void) {}
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#endif
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#endif
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