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23063b378d
This pull request contains one workaround for a Silicon Issue found on all RTL releases prior to 2.20a, which would cause a metastability state on Run/Stop bit. We also have some patches implementing a few extra Standard requests introduced by USB3 spec (Set SEL and Set Isoch Delay), as well as one patch, which has been pending for a long time, implementing LPM support. Last, but not least, we are splitting the host address space out of the dwc3 core driver otherwise xHCI won't be able to request_mem_region() its own address space. This patch is only needed because we are (as we should) re-using the xHCI driver, which is a completely separate module. Together with these three big changes, come a few extra preparatory patches which most move code around, define macros and so on, as well as a fix for Isochronous transfers which hasn't been triggered before. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPo7lXAAoJEIaOsuA1yqRESaIP/AgxZIfOAUbPx0GWLnhub3qr SxaUplweFc9q4KXRLn0kGdY9QArPR3bqW9g8KOTiRCBYRtjpACyMjibAUaAht81h +vLdPt87Slj2c14t1uguWFvgCUYQOCugkVvDIjRg9PCLIuTahm4cIBFqL3RJOHFf 9WCd8JjH9ahr85ZtoCBk9B5bDNn71nS+Yh6/8+Ab90AE4vZ6t8Xx3+wLTHy2CBYQ UH1o61QZreAJ0J3OiUobjqrVbYwz6TM0dFYMjA6ko+OiPRhVOj8/C8aNl/U1whRm +7jjJiWO9aHp+Tu2OAQOBF6ydc3ZLBEiCl9RiE+O9MppmtOykzkTHFm1ZXatCEY7 UUYOy43VXLNlHoz8nidNw6P25hAwwlSijzlyawpihKbIaE8le2MpE6I00AlciM2q BEo4LpluC8Rr6CUUr5W9dPZUexRlzxdAL5nQSJUnJgfEPphpP3x7dWTxUZBaWjq6 akqjgGqVj1QKwMnqL4GILtRgdqWj6WYrw67fYVLHqj8QQla4cgXQ2sHp9/R0imvT nmjiL5ZiuIWWr965DgVHZwqIkdvMpSQb99a1xmptw8lFDGkVJDCssPDdEErbBMwy KmOSaqKeg/Yway05i+Pwo/NUKHQSZeiyuguzniMrF7iYFF1/2hVYRgfpH4V+95w/ Xrnz4uH2YJGQGPddf87P =qgf/ -----END PGP SIGNATURE----- Merge tag 'dwc3-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next usb: dwc3: patches for v3.5 merge window This pull request contains one workaround for a Silicon Issue found on all RTL releases prior to 2.20a, which would cause a metastability state on Run/Stop bit. We also have some patches implementing a few extra Standard requests introduced by USB3 spec (Set SEL and Set Isoch Delay), as well as one patch, which has been pending for a long time, implementing LPM support. Last, but not least, we are splitting the host address space out of the dwc3 core driver otherwise xHCI won't be able to request_mem_region() its own address space. This patch is only needed because we are (as we should) re-using the xHCI driver, which is a completely separate module. Together with these three big changes, come a few extra preparatory patches which most move code around, define macros and so on, as well as a fix for Isochronous transfers which hasn't been triggered before. [ resolved conflicts and build error in drivers/usb/dwc3/gadget.c - gregkh]
2460 lines
60 KiB
C
2460 lines
60 KiB
C
/**
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* gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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/**
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* dwc3_gadget_set_test_mode - Enables USB2 Test Modes
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* @dwc: pointer to our context structure
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* @mode: the mode to set (J, K SE0 NAK, Force Enable)
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*
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* Caller should take care of locking. This function will
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* return 0 on success or -EINVAL if wrong Test Selector
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* is passed
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*/
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int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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reg &= ~DWC3_DCTL_TSTCTRL_MASK;
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switch (mode) {
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case TEST_J:
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case TEST_K:
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case TEST_SE0_NAK:
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case TEST_PACKET:
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case TEST_FORCE_EN:
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reg |= mode << 1;
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break;
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default:
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return -EINVAL;
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}
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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return 0;
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}
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/**
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* dwc3_gadget_set_link_state - Sets USB Link to a particular State
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* @dwc: pointer to our context structure
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* @state: the state to put link into
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*
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* Caller should take care of locking. This function will
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* return 0 on success or -ETIMEDOUT.
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*/
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int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
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{
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int retries = 10000;
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
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/* set requested state */
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reg |= DWC3_DCTL_ULSTCHNGREQ(state);
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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/* wait for a change in DSTS */
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while (--retries) {
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reg = dwc3_readl(dwc->regs, DWC3_DSTS);
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if (DWC3_DSTS_USBLNKST(reg) == state)
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return 0;
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udelay(5);
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}
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dev_vdbg(dwc->dev, "link state change request timed out\n");
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return -ETIMEDOUT;
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}
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/**
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* dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
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* @dwc: pointer to our context structure
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*
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* This function will a best effort FIFO allocation in order
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* to improve FIFO usage and throughput, while still allowing
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* us to enable as many endpoints as possible.
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*
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* Keep in mind that this operation will be highly dependent
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* on the configured size for RAM1 - which contains TxFifo -,
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* the amount of endpoints enabled on coreConsultant tool, and
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* the width of the Master Bus.
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*
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* In the ideal world, we would always be able to satisfy the
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* following equation:
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*
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* ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
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* (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
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*
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* Unfortunately, due to many variables that's not always the case.
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*/
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int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
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{
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int last_fifo_depth = 0;
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int ram1_depth;
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int fifo_size;
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int mdwidth;
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int num;
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if (!dwc->needs_fifo_resize)
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return 0;
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ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
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mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
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/* MDWIDTH is represented in bits, we need it in bytes */
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mdwidth >>= 3;
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/*
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* FIXME For now we will only allocate 1 wMaxPacketSize space
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* for each enabled endpoint, later patches will come to
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* improve this algorithm so that we better use the internal
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* FIFO space
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*/
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for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
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struct dwc3_ep *dep = dwc->eps[num];
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int fifo_number = dep->number >> 1;
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int mult = 1;
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int tmp;
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if (!(dep->number & 1))
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continue;
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if (!(dep->flags & DWC3_EP_ENABLED))
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continue;
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if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
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|| usb_endpoint_xfer_isoc(dep->endpoint.desc))
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mult = 3;
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/*
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* REVISIT: the following assumes we will always have enough
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* space available on the FIFO RAM for all possible use cases.
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* Make sure that's true somehow and change FIFO allocation
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* accordingly.
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*
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* If we have Bulk or Isochronous endpoints, we want
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* them to be able to be very, very fast. So we're giving
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* those endpoints a fifo_size which is enough for 3 full
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* packets
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*/
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tmp = mult * (dep->endpoint.maxpacket + mdwidth);
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tmp += mdwidth;
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fifo_size = DIV_ROUND_UP(tmp, mdwidth);
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fifo_size |= (last_fifo_depth << 16);
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dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
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dep->name, last_fifo_depth, fifo_size & 0xffff);
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dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
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fifo_size);
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last_fifo_depth += (fifo_size & 0xffff);
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}
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return 0;
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}
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void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
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int status)
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{
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struct dwc3 *dwc = dep->dwc;
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if (req->queued) {
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if (req->request.num_mapped_sgs)
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dep->busy_slot += req->request.num_mapped_sgs;
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else
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dep->busy_slot++;
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/*
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* Skip LINK TRB. We can't use req->trb and check for
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* DWC3_TRBCTL_LINK_TRB because it points the TRB we just
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* completed (not the LINK TRB).
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*/
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if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
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usb_endpoint_xfer_isoc(dep->endpoint.desc))
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dep->busy_slot++;
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}
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list_del(&req->list);
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req->trb = NULL;
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if (req->request.status == -EINPROGRESS)
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req->request.status = status;
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usb_gadget_unmap_request(&dwc->gadget, &req->request,
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req->direction);
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dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
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req, dep->name, req->request.actual,
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req->request.length, status);
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spin_unlock(&dwc->lock);
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req->request.complete(&dep->endpoint, &req->request);
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spin_lock(&dwc->lock);
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}
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static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
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{
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switch (cmd) {
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case DWC3_DEPCMD_DEPSTARTCFG:
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return "Start New Configuration";
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case DWC3_DEPCMD_ENDTRANSFER:
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return "End Transfer";
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case DWC3_DEPCMD_UPDATETRANSFER:
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return "Update Transfer";
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case DWC3_DEPCMD_STARTTRANSFER:
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return "Start Transfer";
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case DWC3_DEPCMD_CLEARSTALL:
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return "Clear Stall";
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case DWC3_DEPCMD_SETSTALL:
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return "Set Stall";
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case DWC3_DEPCMD_GETSEQNUMBER:
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return "Get Data Sequence Number";
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case DWC3_DEPCMD_SETTRANSFRESOURCE:
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return "Set Endpoint Transfer Resource";
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case DWC3_DEPCMD_SETEPCONFIG:
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return "Set Endpoint Configuration";
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default:
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return "UNKNOWN command";
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}
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}
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int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
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{
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u32 timeout = 500;
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u32 reg;
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dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
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dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
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if (!(reg & DWC3_DGCMD_CMDACT)) {
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dev_vdbg(dwc->dev, "Command Complete --> %d\n",
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DWC3_DGCMD_STATUS(reg));
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return 0;
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}
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/*
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* We can't sleep here, because it's also called from
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* interrupt context.
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*/
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timeout--;
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if (!timeout)
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return -ETIMEDOUT;
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udelay(1);
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} while (1);
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}
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int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
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unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
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{
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struct dwc3_ep *dep = dwc->eps[ep];
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u32 timeout = 500;
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u32 reg;
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dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
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dep->name,
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dwc3_gadget_ep_cmd_string(cmd), params->param0,
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params->param1, params->param2);
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dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
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dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
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dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
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dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
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if (!(reg & DWC3_DEPCMD_CMDACT)) {
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dev_vdbg(dwc->dev, "Command Complete --> %d\n",
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DWC3_DEPCMD_STATUS(reg));
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return 0;
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}
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/*
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* We can't sleep here, because it is also called from
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* interrupt context.
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*/
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timeout--;
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if (!timeout)
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return -ETIMEDOUT;
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udelay(1);
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} while (1);
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}
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static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
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struct dwc3_trb *trb)
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{
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u32 offset = (char *) trb - (char *) dep->trb_pool;
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return dep->trb_pool_dma + offset;
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}
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static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
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{
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struct dwc3 *dwc = dep->dwc;
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if (dep->trb_pool)
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return 0;
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if (dep->number == 0 || dep->number == 1)
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return 0;
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dep->trb_pool = dma_alloc_coherent(dwc->dev,
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sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
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&dep->trb_pool_dma, GFP_KERNEL);
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if (!dep->trb_pool) {
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dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
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dep->name);
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return -ENOMEM;
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}
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return 0;
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}
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static void dwc3_free_trb_pool(struct dwc3_ep *dep)
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{
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struct dwc3 *dwc = dep->dwc;
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dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
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dep->trb_pool, dep->trb_pool_dma);
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dep->trb_pool = NULL;
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dep->trb_pool_dma = 0;
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}
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static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
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{
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struct dwc3_gadget_ep_cmd_params params;
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u32 cmd;
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memset(¶ms, 0x00, sizeof(params));
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if (dep->number != 1) {
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cmd = DWC3_DEPCMD_DEPSTARTCFG;
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/* XferRscIdx == 0 for ep0 and 2 for the remaining */
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if (dep->number > 1) {
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if (dwc->start_config_issued)
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return 0;
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dwc->start_config_issued = true;
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cmd |= DWC3_DEPCMD_PARAM(2);
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}
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return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
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}
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return 0;
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}
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|
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static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
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const struct usb_endpoint_descriptor *desc,
|
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const struct usb_ss_ep_comp_descriptor *comp_desc)
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|
{
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struct dwc3_gadget_ep_cmd_params params;
|
|
|
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memset(¶ms, 0x00, sizeof(params));
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|
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params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
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| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
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| DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
|
|
|
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params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
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| DWC3_DEPCFG_XFER_NOT_READY_EN;
|
|
|
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if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
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params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
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| DWC3_DEPCFG_STREAM_EVENT_EN;
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dep->stream_capable = true;
|
|
}
|
|
|
|
if (usb_endpoint_xfer_isoc(desc))
|
|
params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
|
|
|
|
/*
|
|
* We are doing 1:1 mapping for endpoints, meaning
|
|
* Physical Endpoints 2 maps to Logical Endpoint 2 and
|
|
* so on. We consider the direction bit as part of the physical
|
|
* endpoint number. So USB endpoint 0x81 is 0x03.
|
|
*/
|
|
params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
|
|
|
|
/*
|
|
* We must use the lower 16 TX FIFOs even though
|
|
* HW might have more
|
|
*/
|
|
if (dep->direction)
|
|
params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
|
|
|
|
if (desc->bInterval) {
|
|
params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
|
|
dep->interval = 1 << (desc->bInterval - 1);
|
|
}
|
|
|
|
return dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
DWC3_DEPCMD_SETEPCONFIG, ¶ms);
|
|
}
|
|
|
|
static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
{
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
|
|
|
|
return dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
|
|
}
|
|
|
|
/**
|
|
* __dwc3_gadget_ep_enable - Initializes a HW endpoint
|
|
* @dep: endpoint to be initialized
|
|
* @desc: USB Endpoint Descriptor
|
|
*
|
|
* Caller should take care of locking
|
|
*/
|
|
static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
|
|
const struct usb_endpoint_descriptor *desc,
|
|
const struct usb_ss_ep_comp_descriptor *comp_desc)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
u32 reg;
|
|
int ret = -ENOMEM;
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
|
ret = dwc3_gadget_start_config(dwc, dep);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
|
struct dwc3_trb *trb_st_hw;
|
|
struct dwc3_trb *trb_link;
|
|
|
|
ret = dwc3_gadget_set_xfer_resource(dwc, dep);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dep->endpoint.desc = desc;
|
|
dep->comp_desc = comp_desc;
|
|
dep->type = usb_endpoint_type(desc);
|
|
dep->flags |= DWC3_EP_ENABLED;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
|
|
reg |= DWC3_DALEPENA_EP(dep->number);
|
|
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
|
|
|
|
if (!usb_endpoint_xfer_isoc(desc))
|
|
return 0;
|
|
|
|
memset(&trb_link, 0, sizeof(trb_link));
|
|
|
|
/* Link TRB for ISOC. The HWO bit is never reset */
|
|
trb_st_hw = &dep->trb_pool[0];
|
|
|
|
trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
|
|
|
|
trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
|
|
trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
|
|
trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
|
|
trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
|
|
static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
{
|
|
struct dwc3_request *req;
|
|
|
|
if (!list_empty(&dep->req_queued))
|
|
dwc3_stop_active_transfer(dwc, dep->number);
|
|
|
|
while (!list_empty(&dep->request_list)) {
|
|
req = next_request(&dep->request_list);
|
|
|
|
dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* __dwc3_gadget_ep_disable - Disables a HW endpoint
|
|
* @dep: the endpoint to disable
|
|
*
|
|
* This function also removes requests which are currently processed ny the
|
|
* hardware and those which are not yet scheduled.
|
|
* Caller should take care of locking.
|
|
*/
|
|
static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
u32 reg;
|
|
|
|
dwc3_remove_requests(dwc, dep);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
|
|
reg &= ~DWC3_DALEPENA_EP(dep->number);
|
|
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
|
|
|
|
dep->stream_capable = false;
|
|
dep->endpoint.desc = NULL;
|
|
dep->comp_desc = NULL;
|
|
dep->type = 0;
|
|
dep->flags = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
|
|
const struct usb_endpoint_descriptor *desc)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static int dwc3_gadget_ep_enable(struct usb_ep *ep,
|
|
const struct usb_endpoint_descriptor *desc)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
struct dwc3 *dwc;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
|
|
pr_debug("dwc3: invalid parameters\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!desc->wMaxPacketSize) {
|
|
pr_debug("dwc3: missing wMaxPacketSize\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dep = to_dwc3_ep(ep);
|
|
dwc = dep->dwc;
|
|
|
|
switch (usb_endpoint_type(desc)) {
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
|
strlcat(dep->name, "-control", sizeof(dep->name));
|
|
break;
|
|
case USB_ENDPOINT_XFER_ISOC:
|
|
strlcat(dep->name, "-isoc", sizeof(dep->name));
|
|
break;
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
strlcat(dep->name, "-bulk", sizeof(dep->name));
|
|
break;
|
|
case USB_ENDPOINT_XFER_INT:
|
|
strlcat(dep->name, "-int", sizeof(dep->name));
|
|
break;
|
|
default:
|
|
dev_err(dwc->dev, "invalid endpoint transfer type\n");
|
|
}
|
|
|
|
if (dep->flags & DWC3_EP_ENABLED) {
|
|
dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
|
|
dep->name);
|
|
return 0;
|
|
}
|
|
|
|
dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_ep_disable(struct usb_ep *ep)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
struct dwc3 *dwc;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
if (!ep) {
|
|
pr_debug("dwc3: invalid parameters\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dep = to_dwc3_ep(ep);
|
|
dwc = dep->dwc;
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED)) {
|
|
dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
|
|
dep->name);
|
|
return 0;
|
|
}
|
|
|
|
snprintf(dep->name, sizeof(dep->name), "ep%d%s",
|
|
dep->number >> 1,
|
|
(dep->number & 1) ? "in" : "out");
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
ret = __dwc3_gadget_ep_disable(dep);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
|
|
gfp_t gfp_flags)
|
|
{
|
|
struct dwc3_request *req;
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
req = kzalloc(sizeof(*req), gfp_flags);
|
|
if (!req) {
|
|
dev_err(dwc->dev, "not enough memory\n");
|
|
return NULL;
|
|
}
|
|
|
|
req->epnum = dep->number;
|
|
req->dep = dep;
|
|
|
|
return &req->request;
|
|
}
|
|
|
|
static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
|
|
struct usb_request *request)
|
|
{
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
|
|
kfree(req);
|
|
}
|
|
|
|
/**
|
|
* dwc3_prepare_one_trb - setup one TRB from one request
|
|
* @dep: endpoint for which this request is prepared
|
|
* @req: dwc3_request pointer
|
|
*/
|
|
static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
|
|
struct dwc3_request *req, dma_addr_t dma,
|
|
unsigned length, unsigned last, unsigned chain)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
struct dwc3_trb *trb;
|
|
|
|
unsigned int cur_slot;
|
|
|
|
dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
|
|
dep->name, req, (unsigned long long) dma,
|
|
length, last ? " last" : "",
|
|
chain ? " chain" : "");
|
|
|
|
trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
|
|
cur_slot = dep->free_slot;
|
|
dep->free_slot++;
|
|
|
|
/* Skip the LINK-TRB on ISOC */
|
|
if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
|
|
usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
|
return;
|
|
|
|
if (!req->trb) {
|
|
dwc3_gadget_move_request_queued(req);
|
|
req->trb = trb;
|
|
req->trb_dma = dwc3_trb_dma_offset(dep, trb);
|
|
}
|
|
|
|
trb->size = DWC3_TRB_SIZE_LENGTH(length);
|
|
trb->bpl = lower_32_bits(dma);
|
|
trb->bph = upper_32_bits(dma);
|
|
|
|
switch (usb_endpoint_type(dep->endpoint.desc)) {
|
|
case USB_ENDPOINT_XFER_CONTROL:
|
|
trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
|
|
break;
|
|
|
|
case USB_ENDPOINT_XFER_ISOC:
|
|
trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
|
|
|
|
/* IOC every DWC3_TRB_NUM / 4 so we can refill */
|
|
if (!(cur_slot % (DWC3_TRB_NUM / 4)))
|
|
trb->ctrl |= DWC3_TRB_CTRL_IOC;
|
|
break;
|
|
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
case USB_ENDPOINT_XFER_INT:
|
|
trb->ctrl = DWC3_TRBCTL_NORMAL;
|
|
break;
|
|
default:
|
|
/*
|
|
* This is only possible with faulty memory because we
|
|
* checked it already :)
|
|
*/
|
|
BUG();
|
|
}
|
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
|
|
trb->ctrl |= DWC3_TRB_CTRL_CSP;
|
|
} else {
|
|
if (chain)
|
|
trb->ctrl |= DWC3_TRB_CTRL_CHN;
|
|
|
|
if (last)
|
|
trb->ctrl |= DWC3_TRB_CTRL_LST;
|
|
}
|
|
|
|
if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
|
|
trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
|
|
|
|
trb->ctrl |= DWC3_TRB_CTRL_HWO;
|
|
}
|
|
|
|
/*
|
|
* dwc3_prepare_trbs - setup TRBs from requests
|
|
* @dep: endpoint for which requests are being prepared
|
|
* @starting: true if the endpoint is idle and no requests are queued.
|
|
*
|
|
* The function goes through the requests list and sets up TRBs for the
|
|
* transfers. The function returns once there are no more TRBs available or
|
|
* it runs out of requests.
|
|
*/
|
|
static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
|
|
{
|
|
struct dwc3_request *req, *n;
|
|
u32 trbs_left;
|
|
u32 max;
|
|
unsigned int last_one = 0;
|
|
|
|
BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
|
|
|
|
/* the first request must not be queued */
|
|
trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
|
|
|
|
/* Can't wrap around on a non-isoc EP since there's no link TRB */
|
|
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
|
|
if (trbs_left > max)
|
|
trbs_left = max;
|
|
}
|
|
|
|
/*
|
|
* If busy & slot are equal than it is either full or empty. If we are
|
|
* starting to process requests then we are empty. Otherwise we are
|
|
* full and don't do anything
|
|
*/
|
|
if (!trbs_left) {
|
|
if (!starting)
|
|
return;
|
|
trbs_left = DWC3_TRB_NUM;
|
|
/*
|
|
* In case we start from scratch, we queue the ISOC requests
|
|
* starting from slot 1. This is done because we use ring
|
|
* buffer and have no LST bit to stop us. Instead, we place
|
|
* IOC bit every TRB_NUM/4. We try to avoid having an interrupt
|
|
* after the first request so we start at slot 1 and have
|
|
* 7 requests proceed before we hit the first IOC.
|
|
* Other transfer types don't use the ring buffer and are
|
|
* processed from the first TRB until the last one. Since we
|
|
* don't wrap around we have to start at the beginning.
|
|
*/
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
dep->busy_slot = 1;
|
|
dep->free_slot = 1;
|
|
} else {
|
|
dep->busy_slot = 0;
|
|
dep->free_slot = 0;
|
|
}
|
|
}
|
|
|
|
/* The last TRB is a link TRB, not used for xfer */
|
|
if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
|
|
return;
|
|
|
|
list_for_each_entry_safe(req, n, &dep->request_list, list) {
|
|
unsigned length;
|
|
dma_addr_t dma;
|
|
|
|
if (req->request.num_mapped_sgs > 0) {
|
|
struct usb_request *request = &req->request;
|
|
struct scatterlist *sg = request->sg;
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, request->num_mapped_sgs, i) {
|
|
unsigned chain = true;
|
|
|
|
length = sg_dma_len(s);
|
|
dma = sg_dma_address(s);
|
|
|
|
if (i == (request->num_mapped_sgs - 1) ||
|
|
sg_is_last(s)) {
|
|
last_one = true;
|
|
chain = false;
|
|
}
|
|
|
|
trbs_left--;
|
|
if (!trbs_left)
|
|
last_one = true;
|
|
|
|
if (last_one)
|
|
chain = false;
|
|
|
|
dwc3_prepare_one_trb(dep, req, dma, length,
|
|
last_one, chain);
|
|
|
|
if (last_one)
|
|
break;
|
|
}
|
|
} else {
|
|
dma = req->request.dma;
|
|
length = req->request.length;
|
|
trbs_left--;
|
|
|
|
if (!trbs_left)
|
|
last_one = 1;
|
|
|
|
/* Is this the last request? */
|
|
if (list_is_last(&req->list, &dep->request_list))
|
|
last_one = 1;
|
|
|
|
dwc3_prepare_one_trb(dep, req, dma, length,
|
|
last_one, false);
|
|
|
|
if (last_one)
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
|
|
int start_new)
|
|
{
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
struct dwc3_request *req;
|
|
struct dwc3 *dwc = dep->dwc;
|
|
int ret;
|
|
u32 cmd;
|
|
|
|
if (start_new && (dep->flags & DWC3_EP_BUSY)) {
|
|
dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
|
|
return -EBUSY;
|
|
}
|
|
dep->flags &= ~DWC3_EP_PENDING_REQUEST;
|
|
|
|
/*
|
|
* If we are getting here after a short-out-packet we don't enqueue any
|
|
* new requests as we try to set the IOC bit only on the last request.
|
|
*/
|
|
if (start_new) {
|
|
if (list_empty(&dep->req_queued))
|
|
dwc3_prepare_trbs(dep, start_new);
|
|
|
|
/* req points to the first request which will be sent */
|
|
req = next_request(&dep->req_queued);
|
|
} else {
|
|
dwc3_prepare_trbs(dep, start_new);
|
|
|
|
/*
|
|
* req points to the first request where HWO changed from 0 to 1
|
|
*/
|
|
req = next_request(&dep->req_queued);
|
|
}
|
|
if (!req) {
|
|
dep->flags |= DWC3_EP_PENDING_REQUEST;
|
|
return 0;
|
|
}
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
params.param0 = upper_32_bits(req->trb_dma);
|
|
params.param1 = lower_32_bits(req->trb_dma);
|
|
|
|
if (start_new)
|
|
cmd = DWC3_DEPCMD_STARTTRANSFER;
|
|
else
|
|
cmd = DWC3_DEPCMD_UPDATETRANSFER;
|
|
|
|
cmd |= DWC3_DEPCMD_PARAM(cmd_param);
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
|
|
if (ret < 0) {
|
|
dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
|
|
|
|
/*
|
|
* FIXME we need to iterate over the list of requests
|
|
* here and stop, unmap, free and del each of the linked
|
|
* requests instead of what we do now.
|
|
*/
|
|
usb_gadget_unmap_request(&dwc->gadget, &req->request,
|
|
req->direction);
|
|
list_del(&req->list);
|
|
return ret;
|
|
}
|
|
|
|
dep->flags |= DWC3_EP_BUSY;
|
|
|
|
if (start_new) {
|
|
dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
|
|
dep->number);
|
|
WARN_ON_ONCE(!dep->res_trans_idx);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
int ret;
|
|
|
|
req->request.actual = 0;
|
|
req->request.status = -EINPROGRESS;
|
|
req->direction = dep->direction;
|
|
req->epnum = dep->number;
|
|
|
|
/*
|
|
* We only add to our list of requests now and
|
|
* start consuming the list once we get XferNotReady
|
|
* IRQ.
|
|
*
|
|
* That way, we avoid doing anything that we don't need
|
|
* to do now and defer it until the point we receive a
|
|
* particular token from the Host side.
|
|
*
|
|
* This will also avoid Host cancelling URBs due to too
|
|
* many NAKs.
|
|
*/
|
|
ret = usb_gadget_map_request(&dwc->gadget, &req->request,
|
|
dep->direction);
|
|
if (ret)
|
|
return ret;
|
|
|
|
list_add_tail(&req->list, &dep->request_list);
|
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
|
|
dep->flags |= DWC3_EP_PENDING_REQUEST;
|
|
|
|
/*
|
|
* There are two special cases:
|
|
*
|
|
* 1. XferNotReady with empty list of requests. We need to kick the
|
|
* transfer here in that situation, otherwise we will be NAKing
|
|
* forever. If we get XferNotReady before gadget driver has a
|
|
* chance to queue a request, we will ACK the IRQ but won't be
|
|
* able to receive the data until the next request is queued.
|
|
* The following code is handling exactly that.
|
|
*
|
|
* 2. XferInProgress on Isoc EP with an active transfer. We need to
|
|
* kick the transfer here after queuing a request, otherwise the
|
|
* core may not see the modified TRB(s).
|
|
*/
|
|
if (dep->flags & DWC3_EP_PENDING_REQUEST) {
|
|
int ret;
|
|
int start_trans = 1;
|
|
u8 trans_idx = dep->res_trans_idx;
|
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
|
|
(dep->flags & DWC3_EP_BUSY)) {
|
|
start_trans = 0;
|
|
WARN_ON_ONCE(!trans_idx);
|
|
} else {
|
|
trans_idx = 0;
|
|
}
|
|
|
|
ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
|
|
if (ret && ret != -EBUSY) {
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
|
|
dep->name);
|
|
}
|
|
};
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
|
|
gfp_t gfp_flags)
|
|
{
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
if (!dep->endpoint.desc) {
|
|
dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
|
|
request, ep->name);
|
|
return -ESHUTDOWN;
|
|
}
|
|
|
|
dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
|
|
request, ep->name, request->length);
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
ret = __dwc3_gadget_ep_queue(dep, req);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
|
|
struct usb_request *request)
|
|
{
|
|
struct dwc3_request *req = to_dwc3_request(request);
|
|
struct dwc3_request *r = NULL;
|
|
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
list_for_each_entry(r, &dep->request_list, list) {
|
|
if (r == req)
|
|
break;
|
|
}
|
|
|
|
if (r != req) {
|
|
list_for_each_entry(r, &dep->req_queued, list) {
|
|
if (r == req)
|
|
break;
|
|
}
|
|
if (r == req) {
|
|
/* wait until it is processed */
|
|
dwc3_stop_active_transfer(dwc, dep->number);
|
|
goto out0;
|
|
}
|
|
dev_err(dwc->dev, "request %p was not queued to %s\n",
|
|
request, ep->name);
|
|
ret = -EINVAL;
|
|
goto out0;
|
|
}
|
|
|
|
/* giveback the request */
|
|
dwc3_gadget_giveback(dep, req, -ECONNRESET);
|
|
|
|
out0:
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
|
|
{
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
struct dwc3 *dwc = dep->dwc;
|
|
int ret;
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
if (value) {
|
|
if (dep->number == 0 || dep->number == 1) {
|
|
/*
|
|
* Whenever EP0 is stalled, we will restart
|
|
* the state machine, thus moving back to
|
|
* Setup Phase
|
|
*/
|
|
dwc->ep0state = EP0_SETUP_PHASE;
|
|
}
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
DWC3_DEPCMD_SETSTALL, ¶ms);
|
|
if (ret)
|
|
dev_err(dwc->dev, "failed to %s STALL on %s\n",
|
|
value ? "set" : "clear",
|
|
dep->name);
|
|
else
|
|
dep->flags |= DWC3_EP_STALL;
|
|
} else {
|
|
if (dep->flags & DWC3_EP_WEDGE)
|
|
return 0;
|
|
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
DWC3_DEPCMD_CLEARSTALL, ¶ms);
|
|
if (ret)
|
|
dev_err(dwc->dev, "failed to %s STALL on %s\n",
|
|
value ? "set" : "clear",
|
|
dep->name);
|
|
else
|
|
dep->flags &= ~DWC3_EP_STALL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
|
|
{
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
ret = __dwc3_gadget_ep_set_halt(dep, value);
|
|
out:
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
|
|
{
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dep->flags |= DWC3_EP_WEDGE;
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return dwc3_gadget_ep_set_halt(ep, 1);
|
|
}
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
|
|
.bLength = USB_DT_ENDPOINT_SIZE,
|
|
.bDescriptorType = USB_DT_ENDPOINT,
|
|
.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
|
|
};
|
|
|
|
static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
|
|
.enable = dwc3_gadget_ep0_enable,
|
|
.disable = dwc3_gadget_ep0_disable,
|
|
.alloc_request = dwc3_gadget_ep_alloc_request,
|
|
.free_request = dwc3_gadget_ep_free_request,
|
|
.queue = dwc3_gadget_ep0_queue,
|
|
.dequeue = dwc3_gadget_ep_dequeue,
|
|
.set_halt = dwc3_gadget_ep_set_halt,
|
|
.set_wedge = dwc3_gadget_ep_set_wedge,
|
|
};
|
|
|
|
static const struct usb_ep_ops dwc3_gadget_ep_ops = {
|
|
.enable = dwc3_gadget_ep_enable,
|
|
.disable = dwc3_gadget_ep_disable,
|
|
.alloc_request = dwc3_gadget_ep_alloc_request,
|
|
.free_request = dwc3_gadget_ep_free_request,
|
|
.queue = dwc3_gadget_ep_queue,
|
|
.dequeue = dwc3_gadget_ep_dequeue,
|
|
.set_halt = dwc3_gadget_ep_set_halt,
|
|
.set_wedge = dwc3_gadget_ep_set_wedge,
|
|
};
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static int dwc3_gadget_get_frame(struct usb_gadget *g)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
u32 reg;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
return DWC3_DSTS_SOFFN(reg);
|
|
}
|
|
|
|
static int dwc3_gadget_wakeup(struct usb_gadget *g)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
|
|
unsigned long timeout;
|
|
unsigned long flags;
|
|
|
|
u32 reg;
|
|
|
|
int ret = 0;
|
|
|
|
u8 link_state;
|
|
u8 speed;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
/*
|
|
* According to the Databook Remote wakeup request should
|
|
* be issued only when the device is in early suspend state.
|
|
*
|
|
* We can check that via USB Link State bits in DSTS register.
|
|
*/
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
|
if (speed == DWC3_DSTS_SUPERSPEED) {
|
|
dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
link_state = DWC3_DSTS_USBLNKST(reg);
|
|
|
|
switch (link_state) {
|
|
case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
|
|
case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
|
|
break;
|
|
default:
|
|
dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
|
|
link_state);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
|
|
if (ret < 0) {
|
|
dev_err(dwc->dev, "failed to put link in Recovery\n");
|
|
goto out;
|
|
}
|
|
|
|
/* write zeroes to Link Change Request */
|
|
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
/* poll until Link State changes to ON */
|
|
timeout = jiffies + msecs_to_jiffies(100);
|
|
|
|
while (!time_after(jiffies, timeout)) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
|
|
/* in HS, means ON */
|
|
if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
|
|
break;
|
|
}
|
|
|
|
if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
|
|
dev_err(dwc->dev, "failed to send remote wakeup\n");
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
|
|
int is_selfpowered)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc->is_selfpowered = !!is_selfpowered;
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
|
|
{
|
|
u32 reg;
|
|
u32 timeout = 500;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
if (is_on) {
|
|
reg &= ~DWC3_DCTL_TRGTULST_MASK;
|
|
reg |= (DWC3_DCTL_RUN_STOP
|
|
| DWC3_DCTL_TRGTULST_RX_DET);
|
|
} else {
|
|
reg &= ~DWC3_DCTL_RUN_STOP;
|
|
}
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
do {
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
if (is_on) {
|
|
if (!(reg & DWC3_DSTS_DEVCTRLHLT))
|
|
break;
|
|
} else {
|
|
if (reg & DWC3_DSTS_DEVCTRLHLT)
|
|
break;
|
|
}
|
|
timeout--;
|
|
if (!timeout)
|
|
break;
|
|
udelay(1);
|
|
} while (1);
|
|
|
|
dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
|
|
dwc->gadget_driver
|
|
? dwc->gadget_driver->function : "no-function",
|
|
is_on ? "connect" : "disconnect");
|
|
}
|
|
|
|
static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
unsigned long flags;
|
|
|
|
is_on = !!is_on;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc3_gadget_run_stop(dwc, is_on);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_gadget_start(struct usb_gadget *g,
|
|
struct usb_gadget_driver *driver)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
struct dwc3_ep *dep;
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
u32 reg;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
if (dwc->gadget_driver) {
|
|
dev_err(dwc->dev, "%s is already bound to %s\n",
|
|
dwc->gadget.name,
|
|
dwc->gadget_driver->driver.name);
|
|
ret = -EBUSY;
|
|
goto err0;
|
|
}
|
|
|
|
dwc->gadget_driver = driver;
|
|
dwc->gadget.dev.driver = &driver->driver;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
reg &= ~(DWC3_DCFG_SPEED_MASK);
|
|
|
|
/**
|
|
* WORKAROUND: DWC3 revision < 2.20a have an issue
|
|
* which would cause metastability state on Run/Stop
|
|
* bit if we try to force the IP to USB2-only mode.
|
|
*
|
|
* Because of that, we cannot configure the IP to any
|
|
* speed other than the SuperSpeed
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000525659: Clock Domain Crossing on DCTL in
|
|
* USB 2.0 Mode
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_220A)
|
|
reg |= DWC3_DCFG_SUPERSPEED;
|
|
else
|
|
reg |= dwc->maximum_speed;
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
dwc->start_config_issued = false;
|
|
|
|
/* Start with SuperSpeed Default */
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
|
|
|
|
dep = dwc->eps[0];
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
goto err0;
|
|
}
|
|
|
|
dep = dwc->eps[1];
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
goto err1;
|
|
}
|
|
|
|
/* begin to receive SETUP packets */
|
|
dwc->ep0state = EP0_SETUP_PHASE;
|
|
dwc3_ep0_out_start(dwc);
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
__dwc3_gadget_ep_disable(dwc->eps[0]);
|
|
|
|
err0:
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_gadget_stop(struct usb_gadget *g,
|
|
struct usb_gadget_driver *driver)
|
|
{
|
|
struct dwc3 *dwc = gadget_to_dwc(g);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
|
|
__dwc3_gadget_ep_disable(dwc->eps[0]);
|
|
__dwc3_gadget_ep_disable(dwc->eps[1]);
|
|
|
|
dwc->gadget_driver = NULL;
|
|
dwc->gadget.dev.driver = NULL;
|
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
static const struct usb_gadget_ops dwc3_gadget_ops = {
|
|
.get_frame = dwc3_gadget_get_frame,
|
|
.wakeup = dwc3_gadget_wakeup,
|
|
.set_selfpowered = dwc3_gadget_set_selfpowered,
|
|
.pullup = dwc3_gadget_pullup,
|
|
.udc_start = dwc3_gadget_start,
|
|
.udc_stop = dwc3_gadget_stop,
|
|
};
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
u8 epnum;
|
|
|
|
INIT_LIST_HEAD(&dwc->gadget.ep_list);
|
|
|
|
for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
dep = kzalloc(sizeof(*dep), GFP_KERNEL);
|
|
if (!dep) {
|
|
dev_err(dwc->dev, "can't allocate endpoint %d\n",
|
|
epnum);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dep->dwc = dwc;
|
|
dep->number = epnum;
|
|
dwc->eps[epnum] = dep;
|
|
|
|
snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
|
|
(epnum & 1) ? "in" : "out");
|
|
dep->endpoint.name = dep->name;
|
|
dep->direction = (epnum & 1);
|
|
|
|
if (epnum == 0 || epnum == 1) {
|
|
dep->endpoint.maxpacket = 512;
|
|
dep->endpoint.ops = &dwc3_gadget_ep0_ops;
|
|
if (!epnum)
|
|
dwc->gadget.ep0 = &dep->endpoint;
|
|
} else {
|
|
int ret;
|
|
|
|
dep->endpoint.maxpacket = 1024;
|
|
dep->endpoint.max_streams = 15;
|
|
dep->endpoint.ops = &dwc3_gadget_ep_ops;
|
|
list_add_tail(&dep->endpoint.ep_list,
|
|
&dwc->gadget.ep_list);
|
|
|
|
ret = dwc3_alloc_trb_pool(dep);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&dep->request_list);
|
|
INIT_LIST_HEAD(&dep->req_queued);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
u8 epnum;
|
|
|
|
for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
dep = dwc->eps[epnum];
|
|
dwc3_free_trb_pool(dep);
|
|
|
|
if (epnum != 0 && epnum != 1)
|
|
list_del(&dep->endpoint.ep_list);
|
|
|
|
kfree(dep);
|
|
}
|
|
}
|
|
|
|
static void dwc3_gadget_release(struct device *dev)
|
|
{
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
}
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
|
|
const struct dwc3_event_depevt *event, int status)
|
|
{
|
|
struct dwc3_request *req;
|
|
struct dwc3_trb *trb;
|
|
unsigned int count;
|
|
unsigned int s_pkt = 0;
|
|
|
|
do {
|
|
req = next_request(&dep->req_queued);
|
|
if (!req) {
|
|
WARN_ON_ONCE(1);
|
|
return 1;
|
|
}
|
|
|
|
trb = req->trb;
|
|
|
|
if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
|
|
/*
|
|
* We continue despite the error. There is not much we
|
|
* can do. If we don't clean it up we loop forever. If
|
|
* we skip the TRB then it gets overwritten after a
|
|
* while since we use them in a ring buffer. A BUG()
|
|
* would help. Lets hope that if this occurs, someone
|
|
* fixes the root cause instead of looking away :)
|
|
*/
|
|
dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
|
|
dep->name, req->trb);
|
|
count = trb->size & DWC3_TRB_SIZE_MASK;
|
|
|
|
if (dep->direction) {
|
|
if (count) {
|
|
dev_err(dwc->dev, "incomplete IN transfer %s\n",
|
|
dep->name);
|
|
status = -ECONNRESET;
|
|
}
|
|
} else {
|
|
if (count && (event->status & DEPEVT_STATUS_SHORT))
|
|
s_pkt = 1;
|
|
}
|
|
|
|
/*
|
|
* We assume here we will always receive the entire data block
|
|
* which we should receive. Meaning, if we program RX to
|
|
* receive 4K but we receive only 2K, we assume that's all we
|
|
* should receive and we simply bounce the request back to the
|
|
* gadget driver for further processing.
|
|
*/
|
|
req->request.actual += req->request.length - count;
|
|
dwc3_gadget_giveback(dep, req, status);
|
|
if (s_pkt)
|
|
break;
|
|
if ((event->status & DEPEVT_STATUS_LST) &&
|
|
(trb->ctrl & DWC3_TRB_CTRL_LST))
|
|
break;
|
|
if ((event->status & DEPEVT_STATUS_IOC) &&
|
|
(trb->ctrl & DWC3_TRB_CTRL_IOC))
|
|
break;
|
|
} while (1);
|
|
|
|
if ((event->status & DEPEVT_STATUS_IOC) &&
|
|
(trb->ctrl & DWC3_TRB_CTRL_IOC))
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
|
|
struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
|
|
int start_new)
|
|
{
|
|
unsigned status = 0;
|
|
int clean_busy;
|
|
|
|
if (event->status & DEPEVT_STATUS_BUSERR)
|
|
status = -ECONNRESET;
|
|
|
|
clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
|
|
if (clean_busy)
|
|
dep->flags &= ~DWC3_EP_BUSY;
|
|
|
|
/*
|
|
* WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
|
|
* See dwc3_gadget_linksts_change_interrupt() for 1st half.
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_183A) {
|
|
u32 reg;
|
|
int i;
|
|
|
|
for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
|
|
struct dwc3_ep *dep = dwc->eps[i];
|
|
|
|
if (!(dep->flags & DWC3_EP_ENABLED))
|
|
continue;
|
|
|
|
if (!list_empty(&dep->req_queued))
|
|
return;
|
|
}
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
reg |= dwc->u1u2;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
dwc->u1u2 = 0;
|
|
}
|
|
}
|
|
|
|
static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
|
|
struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
|
|
{
|
|
u32 uf, mask;
|
|
|
|
if (list_empty(&dep->request_list)) {
|
|
dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
|
|
dep->name);
|
|
return;
|
|
}
|
|
|
|
mask = ~(dep->interval - 1);
|
|
uf = event->parameters & mask;
|
|
/* 4 micro frames in the future */
|
|
uf += dep->interval * 4;
|
|
|
|
__dwc3_gadget_kick_transfer(dep, uf, 1);
|
|
}
|
|
|
|
static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
struct dwc3_event_depevt mod_ev = *event;
|
|
|
|
/*
|
|
* We were asked to remove one request. It is possible that this
|
|
* request and a few others were started together and have the same
|
|
* transfer index. Since we stopped the complete endpoint we don't
|
|
* know how many requests were already completed (and not yet)
|
|
* reported and how could be done (later). We purge them all until
|
|
* the end of the list.
|
|
*/
|
|
mod_ev.status = DEPEVT_STATUS_LST;
|
|
dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
|
|
dep->flags &= ~DWC3_EP_BUSY;
|
|
/* pending requests are ignored and are queued on XferNotReady */
|
|
}
|
|
|
|
static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
u32 param = event->parameters;
|
|
u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
|
|
|
|
switch (cmd_type) {
|
|
case DWC3_DEPCMD_ENDTRANSFER:
|
|
dwc3_process_ep_cmd_complete(dep, event);
|
|
break;
|
|
case DWC3_DEPCMD_STARTTRANSFER:
|
|
dep->res_trans_idx = param & 0x7f;
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
|
|
__func__, cmd_type);
|
|
break;
|
|
};
|
|
}
|
|
|
|
static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
u8 epnum = event->endpoint_number;
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
|
|
dwc3_ep_event_string(event->endpoint_event));
|
|
|
|
if (epnum == 0 || epnum == 1) {
|
|
dwc3_ep0_interrupt(dwc, event);
|
|
return;
|
|
}
|
|
|
|
switch (event->endpoint_event) {
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
|
dep->res_trans_idx = 0;
|
|
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
|
|
dep->name);
|
|
return;
|
|
}
|
|
|
|
dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
|
|
break;
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
|
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
|
|
dep->name);
|
|
return;
|
|
}
|
|
|
|
dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
|
|
break;
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
|
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
|
|
dwc3_gadget_start_isoc(dwc, dep, event);
|
|
} else {
|
|
int ret;
|
|
|
|
dev_vdbg(dwc->dev, "%s: reason %s\n",
|
|
dep->name, event->status &
|
|
DEPEVT_STATUS_TRANSFER_ACTIVE
|
|
? "Transfer Active"
|
|
: "Transfer Not Active");
|
|
|
|
ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
|
|
if (!ret || ret == -EBUSY)
|
|
return;
|
|
|
|
dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
|
|
dep->name);
|
|
}
|
|
|
|
break;
|
|
case DWC3_DEPEVT_STREAMEVT:
|
|
if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
|
|
dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
|
|
dep->name);
|
|
return;
|
|
}
|
|
|
|
switch (event->status) {
|
|
case DEPEVT_STREAMEVT_FOUND:
|
|
dev_vdbg(dwc->dev, "Stream %d found and started\n",
|
|
event->parameters);
|
|
|
|
break;
|
|
case DEPEVT_STREAMEVT_NOTFOUND:
|
|
/* FALLTHROUGH */
|
|
default:
|
|
dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
|
|
}
|
|
break;
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
|
dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
|
|
break;
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
|
dwc3_ep_cmd_compl(dep, event);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void dwc3_disconnect_gadget(struct dwc3 *dwc)
|
|
{
|
|
if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
|
|
spin_unlock(&dwc->lock);
|
|
dwc->gadget_driver->disconnect(&dwc->gadget);
|
|
spin_lock(&dwc->lock);
|
|
}
|
|
}
|
|
|
|
static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
u32 cmd;
|
|
int ret;
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
WARN_ON(!dep->res_trans_idx);
|
|
if (dep->res_trans_idx) {
|
|
cmd = DWC3_DEPCMD_ENDTRANSFER;
|
|
cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
|
|
cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
|
|
memset(¶ms, 0, sizeof(params));
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
|
|
WARN_ON_ONCE(ret);
|
|
dep->res_trans_idx = 0;
|
|
}
|
|
}
|
|
|
|
static void dwc3_stop_active_transfers(struct dwc3 *dwc)
|
|
{
|
|
u32 epnum;
|
|
|
|
for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
struct dwc3_ep *dep;
|
|
|
|
dep = dwc->eps[epnum];
|
|
if (!(dep->flags & DWC3_EP_ENABLED))
|
|
continue;
|
|
|
|
dwc3_remove_requests(dwc, dep);
|
|
}
|
|
}
|
|
|
|
static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
|
|
{
|
|
u32 epnum;
|
|
|
|
for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
|
|
struct dwc3_ep *dep;
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
int ret;
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
if (!(dep->flags & DWC3_EP_STALL))
|
|
continue;
|
|
|
|
dep->flags &= ~DWC3_EP_STALL;
|
|
|
|
memset(¶ms, 0, sizeof(params));
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
|
|
DWC3_DEPCMD_CLEARSTALL, ¶ms);
|
|
WARN_ON_ONCE(ret);
|
|
}
|
|
}
|
|
|
|
static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
|
|
{
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
#if 0
|
|
XXX
|
|
U1/U2 is powersave optimization. Skip it for now. Anyway we need to
|
|
enable it before we can disable it.
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
reg &= ~DWC3_DCTL_INITU1ENA;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
reg &= ~DWC3_DCTL_INITU2ENA;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
#endif
|
|
|
|
dwc3_stop_active_transfers(dwc);
|
|
dwc3_disconnect_gadget(dwc);
|
|
dwc->start_config_issued = false;
|
|
|
|
dwc->gadget.speed = USB_SPEED_UNKNOWN;
|
|
dwc->setup_packet_pending = false;
|
|
}
|
|
|
|
static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
if (on)
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
else
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
}
|
|
|
|
static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
if (on)
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
else
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
}
|
|
|
|
static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
|
|
{
|
|
u32 reg;
|
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
/*
|
|
* WORKAROUND: DWC3 revisions <1.88a have an issue which
|
|
* would cause a missing Disconnect Event if there's a
|
|
* pending Setup Packet in the FIFO.
|
|
*
|
|
* There's no suggested workaround on the official Bug
|
|
* report, which states that "unless the driver/application
|
|
* is doing any special handling of a disconnect event,
|
|
* there is no functional issue".
|
|
*
|
|
* Unfortunately, it turns out that we _do_ some special
|
|
* handling of a disconnect event, namely complete all
|
|
* pending transfers, notify gadget driver of the
|
|
* disconnection, and so on.
|
|
*
|
|
* Our suggested workaround is to follow the Disconnect
|
|
* Event steps here, instead, based on a setup_packet_pending
|
|
* flag. Such flag gets set whenever we have a XferNotReady
|
|
* event on EP0 and gets cleared on XferComplete for the
|
|
* same endpoint.
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000466709: RTL: Device : Disconnect event not
|
|
* generated if setup packet pending in FIFO
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_188A) {
|
|
if (dwc->setup_packet_pending)
|
|
dwc3_gadget_disconnect_interrupt(dwc);
|
|
}
|
|
|
|
/* after reset -> Default State */
|
|
dwc->dev_state = DWC3_DEFAULT_STATE;
|
|
|
|
/* Enable PHYs */
|
|
dwc3_gadget_usb2_phy_power(dwc, true);
|
|
dwc3_gadget_usb3_phy_power(dwc, true);
|
|
|
|
if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
|
|
dwc3_disconnect_gadget(dwc);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
|
|
reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
dwc->test_mode = false;
|
|
|
|
dwc3_stop_active_transfers(dwc);
|
|
dwc3_clear_stall_all_ep(dwc);
|
|
dwc->start_config_issued = false;
|
|
|
|
/* Reset device address to zero */
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
}
|
|
|
|
static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
|
|
{
|
|
u32 reg;
|
|
u32 usb30_clock = DWC3_GCTL_CLK_BUS;
|
|
|
|
/*
|
|
* We change the clock only at SS but I dunno why I would want to do
|
|
* this. Maybe it becomes part of the power saving plan.
|
|
*/
|
|
|
|
if (speed != DWC3_DSTS_SUPERSPEED)
|
|
return;
|
|
|
|
/*
|
|
* RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
|
|
* each time on Connect Done.
|
|
*/
|
|
if (!usb30_clock)
|
|
return;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
}
|
|
|
|
static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
|
|
{
|
|
switch (speed) {
|
|
case USB_SPEED_SUPER:
|
|
dwc3_gadget_usb2_phy_power(dwc, false);
|
|
break;
|
|
case USB_SPEED_HIGH:
|
|
case USB_SPEED_FULL:
|
|
case USB_SPEED_LOW:
|
|
dwc3_gadget_usb3_phy_power(dwc, false);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
|
|
{
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
struct dwc3_ep *dep;
|
|
int ret;
|
|
u32 reg;
|
|
u8 speed;
|
|
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
memset(¶ms, 0x00, sizeof(params));
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
|
|
speed = reg & DWC3_DSTS_CONNECTSPD;
|
|
dwc->speed = speed;
|
|
|
|
dwc3_update_ram_clk_sel(dwc, speed);
|
|
|
|
switch (speed) {
|
|
case DWC3_DCFG_SUPERSPEED:
|
|
/*
|
|
* WORKAROUND: DWC3 revisions <1.90a have an issue which
|
|
* would cause a missing USB3 Reset event.
|
|
*
|
|
* In such situations, we should force a USB3 Reset
|
|
* event by calling our dwc3_gadget_reset_interrupt()
|
|
* routine.
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000483510: RTL: SS : USB3 reset event may
|
|
* not be generated always when the link enters poll
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
dwc3_gadget_reset_interrupt(dwc);
|
|
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
|
|
dwc->gadget.ep0->maxpacket = 512;
|
|
dwc->gadget.speed = USB_SPEED_SUPER;
|
|
break;
|
|
case DWC3_DCFG_HIGHSPEED:
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
|
|
dwc->gadget.ep0->maxpacket = 64;
|
|
dwc->gadget.speed = USB_SPEED_HIGH;
|
|
break;
|
|
case DWC3_DCFG_FULLSPEED2:
|
|
case DWC3_DCFG_FULLSPEED1:
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
|
|
dwc->gadget.ep0->maxpacket = 64;
|
|
dwc->gadget.speed = USB_SPEED_FULL;
|
|
break;
|
|
case DWC3_DCFG_LOWSPEED:
|
|
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
|
|
dwc->gadget.ep0->maxpacket = 8;
|
|
dwc->gadget.speed = USB_SPEED_LOW;
|
|
break;
|
|
}
|
|
|
|
/* Disable unneded PHY */
|
|
dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
|
|
|
|
dep = dwc->eps[0];
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
return;
|
|
}
|
|
|
|
dep = dwc->eps[1];
|
|
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to enable %s\n", dep->name);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Configure PHY via GUSB3PIPECTLn if required.
|
|
*
|
|
* Update GTXFIFOSIZn
|
|
*
|
|
* In both cases reset values should be sufficient.
|
|
*/
|
|
}
|
|
|
|
static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
|
|
{
|
|
dev_vdbg(dwc->dev, "%s\n", __func__);
|
|
|
|
/*
|
|
* TODO take core out of low power mode when that's
|
|
* implemented.
|
|
*/
|
|
|
|
dwc->gadget_driver->resume(&dwc->gadget);
|
|
}
|
|
|
|
static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
|
|
unsigned int evtinfo)
|
|
{
|
|
enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
|
|
|
|
/*
|
|
* WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
|
|
* on the link partner, the USB session might do multiple entry/exit
|
|
* of low power states before a transfer takes place.
|
|
*
|
|
* Due to this problem, we might experience lower throughput. The
|
|
* suggested workaround is to disable DCTL[12:9] bits if we're
|
|
* transitioning from U1/U2 to U0 and enable those bits again
|
|
* after a transfer completes and there are no pending transfers
|
|
* on any of the enabled endpoints.
|
|
*
|
|
* This is the first half of that workaround.
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
|
|
* core send LGO_Ux entering U0
|
|
*/
|
|
if (dwc->revision < DWC3_REVISION_183A) {
|
|
if (next == DWC3_LINK_STATE_U0) {
|
|
u32 u1u2;
|
|
u32 reg;
|
|
|
|
switch (dwc->link_state) {
|
|
case DWC3_LINK_STATE_U1:
|
|
case DWC3_LINK_STATE_U2:
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
u1u2 = reg & (DWC3_DCTL_INITU2ENA
|
|
| DWC3_DCTL_ACCEPTU2ENA
|
|
| DWC3_DCTL_INITU1ENA
|
|
| DWC3_DCTL_ACCEPTU1ENA);
|
|
|
|
if (!dwc->u1u2)
|
|
dwc->u1u2 = reg & u1u2;
|
|
|
|
reg &= ~u1u2;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
dwc->link_state = next;
|
|
|
|
dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
|
|
}
|
|
|
|
static void dwc3_gadget_interrupt(struct dwc3 *dwc,
|
|
const struct dwc3_event_devt *event)
|
|
{
|
|
switch (event->type) {
|
|
case DWC3_DEVICE_EVENT_DISCONNECT:
|
|
dwc3_gadget_disconnect_interrupt(dwc);
|
|
break;
|
|
case DWC3_DEVICE_EVENT_RESET:
|
|
dwc3_gadget_reset_interrupt(dwc);
|
|
break;
|
|
case DWC3_DEVICE_EVENT_CONNECT_DONE:
|
|
dwc3_gadget_conndone_interrupt(dwc);
|
|
break;
|
|
case DWC3_DEVICE_EVENT_WAKEUP:
|
|
dwc3_gadget_wakeup_interrupt(dwc);
|
|
break;
|
|
case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
|
|
dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
|
|
break;
|
|
case DWC3_DEVICE_EVENT_EOPF:
|
|
dev_vdbg(dwc->dev, "End of Periodic Frame\n");
|
|
break;
|
|
case DWC3_DEVICE_EVENT_SOF:
|
|
dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
|
|
break;
|
|
case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
|
|
dev_vdbg(dwc->dev, "Erratic Error\n");
|
|
break;
|
|
case DWC3_DEVICE_EVENT_CMD_CMPL:
|
|
dev_vdbg(dwc->dev, "Command Complete\n");
|
|
break;
|
|
case DWC3_DEVICE_EVENT_OVERFLOW:
|
|
dev_vdbg(dwc->dev, "Overflow\n");
|
|
break;
|
|
default:
|
|
dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
|
|
}
|
|
}
|
|
|
|
static void dwc3_process_event_entry(struct dwc3 *dwc,
|
|
const union dwc3_event *event)
|
|
{
|
|
/* Endpoint IRQ, handle it and return early */
|
|
if (event->type.is_devspec == 0) {
|
|
/* depevt */
|
|
return dwc3_endpoint_interrupt(dwc, &event->depevt);
|
|
}
|
|
|
|
switch (event->type.type) {
|
|
case DWC3_EVENT_TYPE_DEV:
|
|
dwc3_gadget_interrupt(dwc, &event->devt);
|
|
break;
|
|
/* REVISIT what to do with Carkit and I2C events ? */
|
|
default:
|
|
dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
|
|
{
|
|
struct dwc3_event_buffer *evt;
|
|
int left;
|
|
u32 count;
|
|
|
|
count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
|
|
count &= DWC3_GEVNTCOUNT_MASK;
|
|
if (!count)
|
|
return IRQ_NONE;
|
|
|
|
evt = dwc->ev_buffs[buf];
|
|
left = count;
|
|
|
|
while (left > 0) {
|
|
union dwc3_event event;
|
|
|
|
event.raw = *(u32 *) (evt->buf + evt->lpos);
|
|
|
|
dwc3_process_event_entry(dwc, &event);
|
|
/*
|
|
* XXX we wrap around correctly to the next entry as almost all
|
|
* entries are 4 bytes in size. There is one entry which has 12
|
|
* bytes which is a regular entry followed by 8 bytes data. ATM
|
|
* I don't know how things are organized if were get next to the
|
|
* a boundary so I worry about that once we try to handle that.
|
|
*/
|
|
evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
|
|
left -= 4;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
|
|
{
|
|
struct dwc3 *dwc = _dwc;
|
|
int i;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
for (i = 0; i < dwc->num_event_buffers; i++) {
|
|
irqreturn_t status;
|
|
|
|
status = dwc3_process_event_buf(dwc, i);
|
|
if (status == IRQ_HANDLED)
|
|
ret = status;
|
|
}
|
|
|
|
spin_unlock(&dwc->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dwc3_gadget_init - Initializes gadget related registers
|
|
* @dwc: pointer to our controller context structure
|
|
*
|
|
* Returns 0 on success otherwise negative errno.
|
|
*/
|
|
int __devinit dwc3_gadget_init(struct dwc3 *dwc)
|
|
{
|
|
u32 reg;
|
|
int ret;
|
|
int irq;
|
|
|
|
dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
&dwc->ctrl_req_addr, GFP_KERNEL);
|
|
if (!dwc->ctrl_req) {
|
|
dev_err(dwc->dev, "failed to allocate ctrl request\n");
|
|
ret = -ENOMEM;
|
|
goto err0;
|
|
}
|
|
|
|
dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
&dwc->ep0_trb_addr, GFP_KERNEL);
|
|
if (!dwc->ep0_trb) {
|
|
dev_err(dwc->dev, "failed to allocate ep0 trb\n");
|
|
ret = -ENOMEM;
|
|
goto err1;
|
|
}
|
|
|
|
dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
|
|
if (!dwc->setup_buf) {
|
|
dev_err(dwc->dev, "failed to allocate setup buffer\n");
|
|
ret = -ENOMEM;
|
|
goto err2;
|
|
}
|
|
|
|
dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
|
|
DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
|
|
GFP_KERNEL);
|
|
if (!dwc->ep0_bounce) {
|
|
dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
|
|
ret = -ENOMEM;
|
|
goto err3;
|
|
}
|
|
|
|
dev_set_name(&dwc->gadget.dev, "gadget");
|
|
|
|
dwc->gadget.ops = &dwc3_gadget_ops;
|
|
dwc->gadget.max_speed = USB_SPEED_SUPER;
|
|
dwc->gadget.speed = USB_SPEED_UNKNOWN;
|
|
dwc->gadget.dev.parent = dwc->dev;
|
|
dwc->gadget.sg_supported = true;
|
|
|
|
dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
|
|
|
|
dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
|
|
dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
|
|
dwc->gadget.dev.release = dwc3_gadget_release;
|
|
dwc->gadget.name = "dwc3-gadget";
|
|
|
|
/*
|
|
* REVISIT: Here we should clear all pending IRQs to be
|
|
* sure we're starting from a well known location.
|
|
*/
|
|
|
|
ret = dwc3_gadget_init_endpoints(dwc);
|
|
if (ret)
|
|
goto err4;
|
|
|
|
irq = platform_get_irq(to_platform_device(dwc->dev), 0);
|
|
|
|
ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
|
|
"dwc3", dwc);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
|
|
irq, ret);
|
|
goto err5;
|
|
}
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
reg |= DWC3_DCFG_LPM_CAP;
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
/* Enable all but Start and End of Frame IRQs */
|
|
reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
|
|
DWC3_DEVTEN_EVNTOVERFLOWEN |
|
|
DWC3_DEVTEN_CMDCMPLTEN |
|
|
DWC3_DEVTEN_ERRTICERREN |
|
|
DWC3_DEVTEN_WKUPEVTEN |
|
|
DWC3_DEVTEN_ULSTCNGEN |
|
|
DWC3_DEVTEN_CONNECTDONEEN |
|
|
DWC3_DEVTEN_USBRSTEN |
|
|
DWC3_DEVTEN_DISCONNEVTEN);
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
|
|
|
|
ret = device_register(&dwc->gadget.dev);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to register gadget device\n");
|
|
put_device(&dwc->gadget.dev);
|
|
goto err6;
|
|
}
|
|
|
|
ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to register udc\n");
|
|
goto err7;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err7:
|
|
device_unregister(&dwc->gadget.dev);
|
|
|
|
err6:
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
|
|
free_irq(irq, dwc);
|
|
|
|
err5:
|
|
dwc3_gadget_free_endpoints(dwc);
|
|
|
|
err4:
|
|
dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
|
|
dwc->ep0_bounce, dwc->ep0_bounce_addr);
|
|
|
|
err3:
|
|
kfree(dwc->setup_buf);
|
|
|
|
err2:
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
dwc->ep0_trb, dwc->ep0_trb_addr);
|
|
|
|
err1:
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
dwc->ctrl_req, dwc->ctrl_req_addr);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
void dwc3_gadget_exit(struct dwc3 *dwc)
|
|
{
|
|
int irq;
|
|
|
|
usb_del_gadget_udc(&dwc->gadget);
|
|
irq = platform_get_irq(to_platform_device(dwc->dev), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
|
|
free_irq(irq, dwc);
|
|
|
|
dwc3_gadget_free_endpoints(dwc);
|
|
|
|
dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
|
|
dwc->ep0_bounce, dwc->ep0_bounce_addr);
|
|
|
|
kfree(dwc->setup_buf);
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
|
|
dwc->ep0_trb, dwc->ep0_trb_addr);
|
|
|
|
dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
|
|
dwc->ctrl_req, dwc->ctrl_req_addr);
|
|
|
|
device_unregister(&dwc->gadget.dev);
|
|
}
|